projects: ad469x_fmc: Initial version for DE-10Nano

Signed-off-by: Liviu Adace <liviu.adace@analog.com>

projects/ad469x_fmc/common/ad469x_qsys.tcl

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+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+# receive dma
+set_instance_parameter_value sys_hps {F2SDRAM_Width} {128 64}
+
+add_instance axi_dmac_0 axi_dmac
+set_instance_parameter_value axi_dmac_0 {DMA_TYPE_SRC} {1}
+set_instance_parameter_value axi_dmac_0 {DMA_TYPE_DEST} {0}
+set_instance_parameter_value axi_dmac_0 {CYCLIC} {0}
+set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_SRC} {32}
+set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_DEST} {64}
+
+# axi_spi_engine
+
+add_instance axi_spi_engine_0 axi_spi_engine
+set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1}
+set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH}    {32}
+set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE}    {0}
+set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI}    {1}
+set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD}   {1}
+
+# spi_engine_execution
+
+add_instance spi_engine_execution_0 spi_engine_execution
+set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32}
+set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {1}
+set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0}
+
+# spi_engine_interconnect
+
+add_instance spi_engine_interconnect_0 spi_engine_interconnect
+set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32}
+set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {1}
+
+# bridges
+
+add_instance clock_bridge_0 altera_clock_bridge
+set_instance_parameter_value clock_bridge_0 {EXPLICIT_CLOCK_RATE} {0.0}
+set_instance_parameter_value clock_bridge_0 {NUM_CLOCK_OUTPUTS} {1}
+
+add_instance reset_bridge_0 altera_reset_bridge
+set_instance_parameter_value reset_bridge_0 {ACTIVE_LOW_RESET} {1}
+set_instance_parameter_value reset_bridge_0 {NUM_RESET_OUTPUTS} {1}
+set_instance_parameter_value reset_bridge_0 {SYNCHRONOUS_EDGES} {none}
+set_instance_parameter_value reset_bridge_0 {USE_RESET_REQUEST} {0}
+
+# spi_engine_offload
+
+add_instance spi_engine_offload_0 spi_engine_offload
+set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG}    {1}
+set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0}
+set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH}    {32}
+set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI}    {1}
+
+# axi pwm gen
+
+add_instance ad469x_trigger_gen axi_pwm_gen
+set_instance_parameter_value ad469x_trigger_gen {N_PWMS} {1}
+set_instance_parameter_value ad469x_trigger_gen {PULSE_0_PERIOD} {$sampling_cycle}
+set_instance_parameter_value ad469x_trigger_gen {PULSE_0_WIDTH} {1}
+
+# exported interface
+
+add_interface ad469x_spi_sclk       clock source
+add_interface ad469x_spi_cs         conduit end
+add_interface ad469x_spi_sdi        conduit end
+add_interface ad469x_spi_sdo        conduit end
+add_interface ad469x_spi_trigger    conduit end
+add_interface ad469x_spi_cnv        conduit end
+add_interface ad469x_spi_resetn     reset source
+
+set_interface_property ad469x_spi_cs      EXPORT_OF spi_engine_execution_0.if_cs
+set_interface_property ad469x_spi_sclk    EXPORT_OF spi_engine_execution_0.if_sclk
+set_interface_property ad469x_spi_sdi     EXPORT_OF spi_engine_execution_0.if_sdi
+set_interface_property ad469x_spi_sdo     EXPORT_OF spi_engine_execution_0.if_sdo
+set_interface_property ad469x_spi_trigger EXPORT_OF spi_engine_offload_0.if_trigger
+set_interface_property ad469x_spi_cnv     EXPORT_OF ad469x_trigger_gen.if_pwm_0
+set_interface_property ad469x_spi_resetn  EXPORT_OF reset_bridge_0.out_reset
+
+
+add_connection axi_spi_engine_0.if_spi_resetn reset_bridge_0.in_reset
+
+# clocks
+
+add_interface ad469x_spi_clk        clock source
+set_interface_property ad469x_spi_clk     EXPORT_OF clock_bridge_0.out_clk
+
+add_connection sys_clk.clk ad469x_trigger_gen.s_axi_clock
+add_connection sys_clk.clk axi_spi_engine_0.s_axi_clock
+add_connection sys_clk.clk axi_dmac_0.s_axi_clock
+
+add_connection sys_dma_clk.clk ad469x_trigger_gen.if_ext_clk
+add_connection sys_dma_clk.clk spi_engine_execution_0.if_clk
+add_connection sys_dma_clk.clk spi_engine_interconnect_0.if_clk
+add_connection sys_dma_clk.clk axi_spi_engine_0.if_spi_clk
+add_connection sys_dma_clk.clk spi_engine_offload_0.if_ctrl_clk
+add_connection sys_dma_clk.clk spi_engine_offload_0.if_spi_clk
+add_connection sys_dma_clk.clk axi_dmac_0.if_s_axis_aclk
+add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock
+add_connection sys_dma_clk.clk clock_bridge_0.in_clk
+
+# resets
+
+add_connection sys_clk.clk_reset ad469x_trigger_gen.s_axi_reset
+
+add_connection sys_clk.clk_reset axi_spi_engine_0.s_axi_reset
+add_connection sys_clk.clk_reset axi_dmac_0.s_axi_reset
+
+add_connection axi_spi_engine_0.if_spi_resetn spi_engine_execution_0.if_resetn
+add_connection axi_spi_engine_0.if_spi_resetn spi_engine_interconnect_0.if_resetn
+add_connection axi_spi_engine_0.if_spi_resetn spi_engine_offload_0.if_spi_resetn
+
+add_connection sys_dma_clk.clk_reset axi_dmac_0.m_dest_axi_reset
+
+# interfaces
+
+add_connection spi_engine_interconnect_0.m_cmd spi_engine_execution_0.cmd
+add_connection spi_engine_execution_0.sdi_data spi_engine_interconnect_0.m_sdi
+add_connection spi_engine_interconnect_0.m_sdo spi_engine_execution_0.sdo_data
+add_connection spi_engine_execution_0.sync spi_engine_interconnect_0.m_sync
+
+add_connection axi_spi_engine_0.cmd spi_engine_interconnect_0.s0_cmd
+add_connection spi_engine_interconnect_0.s0_sdi axi_spi_engine_0.sdi_data
+add_connection axi_spi_engine_0.sdo_data spi_engine_interconnect_0.s0_sdo
+add_connection spi_engine_interconnect_0.s0_sync axi_spi_engine_0.sync
+
+add_connection spi_engine_offload_0.cmd spi_engine_interconnect_0.s1_cmd
+add_connection spi_engine_interconnect_0.s1_sdi  spi_engine_offload_0.sdi_data
+add_connection spi_engine_offload_0.sdo_data spi_engine_interconnect_0.s1_sdo
+add_connection spi_engine_interconnect_0.s1_sync spi_engine_offload_0.sync
+
+add_connection spi_engine_offload_0.ctrl_cmd_wr       axi_spi_engine_0.offload0_cmd
+add_connection spi_engine_offload_0.ctrl_sdo_wr       axi_spi_engine_0.offload0_sdo
+add_connection spi_engine_offload_0.if_ctrl_enable    axi_spi_engine_0.if_offload0_enable
+add_connection spi_engine_offload_0.if_ctrl_enabled   axi_spi_engine_0.if_offload0_enabled
+add_connection spi_engine_offload_0.if_ctrl_mem_reset axi_spi_engine_0.if_offload0_mem_reset
+add_connection spi_engine_offload_0.status_sync       axi_spi_engine_0.offload_sync
+
+add_connection spi_engine_offload_0.offload_sdi axi_dmac_0.s_axis
+
+# cpu interconnects
+
+ad_cpu_interconnect 0x00020000 axi_dmac_0.s_axi
+ad_cpu_interconnect 0x00030000 axi_spi_engine_0.s_axi
+ad_cpu_interconnect 0x00040000 ad469x_trigger_gen.s_axi
+
+# dma interconnect
+
+ad_dma_interconnect axi_dmac_0.m_dest_axi
+
+#interrupts
+
+ad_cpu_interrupt 4 axi_dmac_0.interrupt_sender
+ad_cpu_interrupt 5 axi_spi_engine_0.interrupt_sender

projects/ad469x_fmc/de10nano/Makefile

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+####################################################################################
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+PROJECT_NAME := ad469x_fmc_de10nano
+
+M_DEPS += ../common/ad469x_qsys.tcl
+M_DEPS += ../../scripts/adi_pd.tcl
+M_DEPS += ../../common/de10nano/de10nano_system_qsys.tcl
+M_DEPS += ../../common/de10nano/de10nano_system_assign.tcl
+M_DEPS += ../../../library/util_cdc/sync_bits.v
+M_DEPS += ../../../library/common/ad_edge_detect.v
+
+LIB_DEPS += axi_dmac
+LIB_DEPS += axi_hdmi_tx
+LIB_DEPS += axi_sysid
+LIB_DEPS += spi_engine/axi_spi_engine
+LIB_DEPS += spi_engine/spi_engine_execution
+LIB_DEPS += spi_engine/spi_engine_interconnect
+LIB_DEPS += spi_engine/spi_engine_offload
+LIB_DEPS += sysid_rom
+LIB_DEPS += axi_pwm_gen
+
+include ../../scripts/project-intel.mk

projects/ad469x_fmc/de10nano/system_constr.sdc

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+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+create_clock -period "20.000 ns"  -name sys_clk     [get_ports {sys_clk}]
+create_clock -period "16.666 ns"  -name usb1_clk    [get_ports {usb1_clk}]

projects/ad469x_fmc/de10nano/system_project.tcl

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+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+set REQUIRED_QUARTUS_VERSION 22.1std.0
+set QUARTUS_PRO_ISUSED 0
+source ../../../scripts/adi_env.tcl
+source ../../scripts/adi_project_intel.tcl
+
+adi_project ad469x_fmc_de10nano
+
+source $ad_hdl_dir/projects/common/de10nano/de10nano_system_assign.tcl
+
+# files
+
+set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/ad_edge_detect.v
+set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/util_cdc/sync_bits.v
+
+# ad469x interface
+
+set_location_assignment PIN_AH8  -to ad469x_spi_cnv        ; ##   P4.7 Arduino_IO07
+set_location_assignment PIN_AG10 -to ad469x_resetn         ; ##   P4.5 Arduino_IO02
+
+set_location_assignment PIN_AE15 -to ad469x_busy_alt_gp0   ; ##   P3.2 Arduino_IO09
+
+set_location_assignment PIN_AF15 -to ad469x_spi_cs         ; ##   P3.3 Arduino_IO10
+set_location_assignment PIN_AG16 -to ad469x_spi_sdo        ; ##   P3.4 Arduino_IO11
+set_location_assignment PIN_AH11 -to ad469x_spi_sdi        ; ##   P3.5 Arduino_IO12
+set_location_assignment PIN_AH12 -to ad469x_spi_sclk       ; ##   P3.6 Arduino_IO13
+
+set_location_assignment PIN_AH9   -to i2c_sda              ; ##   P3.9 Arduino_IO14
+set_location_assignment PIN_AG11  -to i2c_scl              ; ##   P3.10 Arduino_IO15
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ad469x_spi_cnv
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ad469x_resetn
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ad469x_busy_alt_gp0
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ad469x_spi_cs
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ad469x_spi_sdo
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ad469x_spi_sdi
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ad469x_spi_sclk
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2c_scl
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2c_sda
+
+execute_flow -compile

projects/ad469x_fmc/de10nano/system_qsys.tcl

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+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source $ad_hdl_dir/projects/scripts/adi_pd.tcl
+source $ad_hdl_dir/projects/common/de10nano/de10nano_system_qsys.tcl
+
+if [info exists ad_project_dir] {
+  source ../../common/ad469x_qsys.tcl
+} else {
+  source ../common/ad469x_qsys.tcl
+}
+
+#system ID
+set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9}
+set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9}
+
+set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt"
+
+sysid_gen_sys_init_file;