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projects/ad9265_fmc: Solved the requested changes
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Updated the HDL project and the documentation.

Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
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cristianmihaipopa committed Feb 6, 2024
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24 changes: 6 additions & 18 deletions docs/projects/ad9265_fmc/index.rst
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Expand Up @@ -58,25 +58,20 @@ Block diagram
Clock scheme
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

There are 3 ways to configure the clock source for :adi:`AD9265` (some
modification maybe necessary).
There are 3 ways to configure the clock source for :adi:`AD9265`:

- External passive clock (default)
- Optional active clock path using the :adi:`AD9517`
- Optional oscillator

For more details, check :adi:`AD9265` schematic.


CPU/Memory interconnects addresses
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

The addresses are dependent on the architecture of the FPGA, having an offset
added to the base address from HDL (see more at :ref:`architecture`).

Depending on the values of parameters $INTF_CFG, $ADI_PHY_SEL and $TDD_SUPPORT,
some IPs are instatiated and some are not.

Check-out the table below to find out the conditions.

==================== ===============
Expand All @@ -89,9 +84,6 @@ axi_ad9265_dma 0x44A30000
SPI connections
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

THESE ARE JUST EXAMPLES!!!
USE WHICHEVER FITS BEST YOUR CASE

.. list-table::
:widths: 25 25 25 25
:header-rows: 1
Expand All @@ -114,10 +106,6 @@ Interrupts

Below are the Programmable Logic interrupts used in this project.

You have many ways of writing this table: as a list-table or really to draw
it. Take a look in the .rst of this page to see how they're written and
which suits best your case.

.. list-table::
:widths: 30 10 15 15
:header-rows: 1
Expand All @@ -141,8 +129,8 @@ the source you must
`clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
the HDL repository.

Then go to the project location(**projects/ad9265_fmc/carrier**) and run the make command by
typing in your command prompt(this example :adi:`ZC706``):
Then go to the project location (**projects/ad9265_fmc/carrier**) and run the make command by
typing in your command prompt(this example :xilinx:`ZC706`):

**Linux/Cygwin/WSL**

Expand Down Expand Up @@ -174,7 +162,7 @@ Hardware related
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

- Product datasheets: :adi:`AD9265`
- :dokuwiki:`Evaluating AD9434, user guide <resources/eval/ad9265-fmc-125ebz>`
- :dokuwiki:`Evaluating AD9265, user guide <resources/eval/ad9265-fmc-125ebz>`

HDL related
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Expand All @@ -189,7 +177,7 @@ HDL related
- Source code link
- Documentation link
* - AXI_AD9265
- :git-hdl:`library/axi_ad9434 <library/axi_ad9265>`
- :git-hdl:`library/axi_ad9265 <library/axi_ad9265>`
- ---
* - AXI_DMAC
- :git-hdl:`library/axi_dmac <library/axi_dmac>`
Expand All @@ -198,7 +186,7 @@ HDL related
- :git-hdl:`library/axi_clkgen <library/axi_clkgen>`
- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_clkgen>`
* - AXI_HDMI_TX
- :git-hdl:`library/axi_hdmi_tx <library/axi_ad9434>`
- :git-hdl:`library/axi_hdmi_tx <library/axi_hdmi_tx>`
- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_hdmi_tx>`
* - AXI_SPDIF_TX
- :git-hdl:`library/axi_spdif_tx <library/axi_spdif_tx>`
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32 changes: 32 additions & 0 deletions projects/ad9265_fmc/common/ad9265_fmc.txt
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FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination

# ad9265

H4 CLK0_M2C_P DCO+_GLOBAL adc_clk_in_p LVDS_25 DIFF_TERM TRUE
H5 CLK0_M2C_N DCO-_GLOBAL adc_clk_in_n LVDS_25 DIFF_TERM TRUE

D14 LA09_P D0/1+ adc_data_in_p[0] LVDS_25 DIFF_TERM TRUE
D15 LA09_N D0/1- adc_data_in_n[0] LVDS_25 DIFF_TERM TRUE
C10 LA06_P D2/3+ adc_data_in_p[1] LVDS_25 DIFF_TERM TRUE
C11 LA06_N D2/3- adc_data_in_n[1] LVDS_25 DIFF_TERM TRUE
H13 LA07_P D4/5+ adc_data_in_p[2] LVDS_25 DIFF_TERM TRUE
H14 LA07_N D4/5- adc_data_in_n[2] LVDS_25 DIFF_TERM TRUE
G12 LA08_P D6/7+ adc_data_in_p[3] LVDS_25 DIFF_TERM TRUE
G13 LA08_N D6/7- adc_data_in_n[3] LVDS_25 DIFF_TERM TRUE
H10 LA04_P D8/9+ adc_data_in_p[4] LVDS_25 DIFF_TERM TRUE
H11 LA04_N D8/9- adc_data_in_n[4] LVDS_25 DIFF_TERM TRUE
D11 LA05_P D10/11+ adc_data_in_p[5] LVDS_25 DIFF_TERM TRUE
D12 LA05_N D10/11- adc_data_in_n[5] LVDS_25 DIFF_TERM TRUE
H7 LA02_P D12/13+ adc_data_in_p[6] LVDS_25 DIFF_TERM TRUE
H8 LA02_N D12/13- adc_data_in_n[6] LVDS_25 DIFF_TERM TRUE
G9 LA03_P D14/15+ adc_data_in_p[7] LVDS_25 DIFF_TERM TRUE
G10 LA03_N D14/15- adc_data_in_n[7] LVDS_25 DIFF_TERM TRUE
D8 LA01_CC_P OR+ adc_data_or_p LVDS_25 DIFF_TERM TRUE
D9 LA01_CC_N OR- adc_data_or_n LVDS_25 DIFF_TERM TRUE

# spi

G36 LA33_P AD9517_CSB spi_csn_clk LVCMOS25 #N/A
G37 LA33_N CSB spi_csn_adc LVCMOS25 #N/A
H37 LA32_P SDIO spi_sdio LVCMOS25 #N/A
H38 LA32_N SCLK spi_clk LVCMOS25 #N/A
2 changes: 1 addition & 1 deletion projects/ad9265_fmc/zed/Makefile
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####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
## Copyright (c) 2018 - 2024 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
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2 changes: 1 addition & 1 deletion projects/ad9265_fmc/zed/system_bd.tcl
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###############################################################################
## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

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55 changes: 28 additions & 27 deletions projects/ad9265_fmc/zed/system_constr.xdc
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###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

# ad9265

set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## H4 FMC_CLK0_M2C_P IO_L12P_T1_MRCC_34
set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## H5 FMC_CLK0_M2C_N IO_L12N_T1_MRCC_34

set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## D14 FMC_LA09_P IO_L17P_T2_34
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## D15 FMC_LA09_N IO_L17N_T2_34
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## C10 FMC_LA06_P IO_L10P_T1_34
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## C11 FMC_LA06_N IO_L10N_T1_34
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## H13 FMC_LA07_P IO_L21P_T3_DQS_34
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## H14 FMC_LA07_N IO_L21N_T3_DQS_34
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## G12 FMC_LA08_P IO_L8P_T1_34
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## G13 FMC_LA08_N IO_L8N_T1_34
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## H10 FMC_LA04_P IO_L15P_T2_DQS_34
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## H11 FMC_LA04_N IO_L15N_T2_DQS_34
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## D11 FMC_LA05_P IO_L7P_T1_34
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## D12 FMC_LA05_N IO_L7N_T1_34
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## H7 FMC_LA02_P IO_L20P_T3_34
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## H8 FMC_LA02_N IO_L20N_T3_34
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## G9 FMC_LA03_P IO_L16P_T2_34
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## G10 FMC_LA03_N IO_L16N_T2_34
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_or_p] ; ## D8 FMC_LA01_CC_P IO_L14P_T2_SRCC_34
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_or_n] ; ## D9 FMC_LA01_CC_N IO_L14N_T2_SRCC_34
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports adc_clk_in_p]
set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports adc_clk_in_n]

set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {adc_data_in_p[0]}]
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {adc_data_in_n[0]}]
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {adc_data_in_p[1]}]
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {adc_data_in_n[1]}]
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {adc_data_in_p[2]}]
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {adc_data_in_n[2]}]
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {adc_data_in_p[3]}]
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {adc_data_in_n[3]}]
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {adc_data_in_p[4]}]
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {adc_data_in_n[4]}]
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {adc_data_in_p[5]}]
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {adc_data_in_n[5]}]
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {adc_data_in_p[6]}]
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {adc_data_in_n[6]}]
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {adc_data_in_p[7]}]
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {adc_data_in_n[7]}]
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports adc_data_or_p]
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports adc_data_or_n]

# spi

set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## G36 FMC_LA33_P IO_L18P_T2_AD13P_35
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## G37 FMC_LA33_N IO_L18N_T2_AD13N_35
set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## H37 FMC_LA32_P IO_L15P_T2_DQS_AD12P_35
set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H38 FMC_LA32_N IO_L15N_T2_DQS_AD12N_35
set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk]
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc]
set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports spi_sdio]
set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports spi_clk]

# clocks

create_clock -name adc_clk -period 3.33 [get_ports adc_clk_in_p]
create_clock -period 3.330 -name adc_clk [get_ports adc_clk_in_p]

2 changes: 1 addition & 1 deletion projects/ad9265_fmc/zed/system_project.tcl
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###############################################################################
## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

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3 changes: 1 addition & 2 deletions projects/ad9265_fmc/zed/system_top.v
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// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -98,7 +98,6 @@ module system_top (

// internal signals

wire [ 1:0] spi_csn; // not sure if it's necessearry
wire spi_miso;
wire spi_mosi;

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