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ad4630_fmc: Initial version of ADAQ4224 w/ and w/o fully isolated pow…
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…er supply

Signed-off-by: Liviu Adace <liviu.adace@analog.com>
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@ladace
ladace committed Apr 2, 2024
1 parent 1074779 commit 28709be
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20 changes: 20 additions & 0 deletions projects/ad4630_fmc/common/ad4030_fmc.txt
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# ad4030

FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination

G6 LA00_P_CC SCK_FMC ad463x_spi_sclk LVCMOS25 #N/A
G7 LA00_N_CC CS_FMC ad463x_spi_cs LVCMOS25 #N/A
G9 LA03_P SDO2_FMC ad463x_spi_sdi[2] LVCMOS25 #N/A
G10 LA03_N SDO3_FMC ad463x_spi_sdi[3] LVCMOS25 #N/A
H4 CLK0_M2C_P CLK ad463x_ext_clk LVCMOS25 #N/A
H7 LA02_P SDO0_FMC ad463x_spi_sdi[0] LVCMOS25 #N/A
H8 LA02_N SDO1_FMC ad463x_spi_sdi[1] LVCMOS25 #N/A
H10 LA04_P SDO4_FMC ad463x_spi_sdi[4] LVCMOS25 #N/A
H11 LA04_N SDO5_FMC ad463x_spi_sdi[5] LVCMOS25 #N/A
D8 LA01_P_CC CNV_FMC ad463x_cnv LVCMOS25 #N/A
D9 LA01_N_CC RESET_FMC ad463x_resetn LVCMOS25 #N/A
D11 LA05_P SDO6_FMC ad463x_spi_sdi[6] LVCMOS25 #N/A
D12 LA05_N SDO7_FMC ad463x_spi_sdi[7] LVCMOS25 #N/A
D20 LA17_P_CC SCK_OUT_FMC ad463x_echo_sclk LVCMOS25 #N/A
C11 LA06_N SDI_FMC ad463x_spi_sdo LVCMOS25 #N/A
C22 LA18_P_CC BUSY_FMC ad463x_busy LVCMOS25 #N/A
17 changes: 17 additions & 0 deletions projects/ad4630_fmc/common/ad463x_bd.tcl
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Expand Up @@ -21,6 +21,9 @@ set cnv_ref_clk 100
# NOTE: this is a default value, software may or may not change this
set adc_sampling_rate 1000000

# specify the MAX17687 and LT8608 SYNC signal frequency (400KHz)
set max17687_sync_freq 400000

#create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 ad463x_spi

create_bd_port -dir O ad463x_spi_sclk
Expand All @@ -34,6 +37,8 @@ create_bd_port -dir I ad463x_busy
create_bd_port -dir O ad463x_cnv
create_bd_port -dir I ad463x_ext_clk

create_bd_port -dir O max17687_sync_clk

## To support the 2MSPS (SCLK == 80 MHz), set the spi clock to 160 MHz

ad_ip_instance axi_clkgen spi_clkgen
Expand Down Expand Up @@ -70,6 +75,9 @@ ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_axi_regmap CONFIG.CFG_INFO_3
## CNV generator; the actual sample rate will be PULSE_PERIOD * (1/cnv_ref_clk)
set sampling_cycle [expr int(ceil(double($cnv_ref_clk * 1000000) / $adc_sampling_rate))]

## setup the pulse period for the MAX17687 and LT8608 SYNC signal
set max17687_cycle [expr int(ceil(double($cnv_ref_clk * 1000000) / $max17687_sync_freq))]

ad_ip_instance axi_pwm_gen cnv_generator
ad_ip_parameter cnv_generator CONFIG.N_PWMS 2
ad_ip_parameter cnv_generator CONFIG.PULSE_0_PERIOD $sampling_cycle
Expand All @@ -78,6 +86,11 @@ ad_ip_parameter cnv_generator CONFIG.PULSE_1_PERIOD $sampling_cycle
ad_ip_parameter cnv_generator CONFIG.PULSE_1_WIDTH 1
ad_ip_parameter cnv_generator CONFIG.PULSE_1_OFFSET 1

ad_ip_instance axi_pwm_gen sync_generator
ad_ip_parameter sync_generator CONFIG.N_PWMS 1
ad_ip_parameter sync_generator CONFIG.PULSE_0_PERIOD $max17687_cycle
ad_ip_parameter sync_generator CONFIG.PULSE_0_WIDTH [expr int(ceil(double($max17687_cycle) / 2))]

ad_ip_instance spi_axis_reorder data_reorder
ad_ip_parameter data_reorder CONFIG.NUM_OF_LANES $NUM_OF_SDI

Expand Down Expand Up @@ -171,15 +184,18 @@ if {$CAPTURE_ZONE == 1} {

}
ad_connect ad463x_cnv cnv_generator/pwm_1
ad_connect max17687_sync_clk sync_generator/pwm_0

# clocks

ad_connect $sys_cpu_clk $hier_spi_engine/clk
ad_connect $sys_cpu_clk cnv_generator/s_axi_aclk
ad_connect $sys_cpu_clk sync_generator/s_axi_aclk
ad_connect spi_clk $hier_spi_engine/spi_clk
ad_connect spi_clk data_reorder/axis_aclk
ad_connect spi_clk axi_ad463x_dma/s_axis_aclk
ad_connect ad463x_ext_clk cnv_generator/ext_clk
ad_connect ad463x_ext_clk sync_generator/ext_clk

# resets

Expand All @@ -201,6 +217,7 @@ ad_connect axi_ad463x_dma/s_axis data_reorder/m_axis

ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
ad_cpu_interconnect 0x44b00000 cnv_generator
ad_cpu_interconnect 0x44c00000 sync_generator
ad_cpu_interconnect 0x44a30000 axi_ad463x_dma
ad_cpu_interconnect 0x44a70000 spi_clkgen

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27 changes: 27 additions & 0 deletions projects/ad4630_fmc/common/adaq42xx_fmc.txt
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# adaq42xx

FMC_pin FMC_port Schematic_name System_top_name IOSTANDARD Termination

G6 LA00_P_CC SCK_FMC ad463x_spi_sclk LVCMOS25 #N/A
G7 LA00_N_CC CS_FMC ad463x_spi_cs LVCMOS25 #N/A
G9 LA03_P SDO2_FMC ad463x_spi_sdi[2] LVCMOS25 #N/A
G10 LA03_N SDO3_FMC ad463x_spi_sdi[3] LVCMOS25 #N/A
H4 CLK0_M2C_P CLK ad463x_ext_clk LVCMOS25 #N/A
H7 LA02_P SDO0_FMC ad463x_spi_sdi[0] LVCMOS25 #N/A
H8 LA02_N SDO1_FMC ad463x_spi_sdi[1] LVCMOS25 #N/A
H10 LA04_P SDO4_FMC ad463x_spi_sdi[4] LVCMOS25 #N/A
H11 LA04_N SDO5_FMC ad463x_spi_sdi[5] LVCMOS25 #N/A
D8 LA01_P_CC CNV_FMC ad463x_cnv LVCMOS25 #N/A
D9 LA01_N_CC RESET_FMC ad463x_resetn LVCMOS25 #N/A
D11 LA05_P SDO6_FMC ad463x_spi_sdi[6] LVCMOS25 #N/A
D12 LA05_N SDO7_FMC ad463x_spi_sdi[7] LVCMOS25 #N/A
D20 LA17_P_CC SCK_OUT_FMC ad463x_echo_sclk LVCMOS25 #N/A
C11 LA06_N SDI_FMC ad463x_spi_sdo LVCMOS25 #N/A
C22 LA18_P_CC BUSY_FMC ad463x_busy LVCMOS25 #N/A

G12 LA08_P MUX_A0 adaq42xx_pgia_mux[0] LVCMOS25 #N/A
G13 LA08_N MUX_A1 adaq42xx_pgia_mux[1] LVCMOS25 #N/A

H13 LA07_P RST max17687_rst LVCMOS25 #N/A
H14 LA07_N EN max17687_en LVCMOS25 #N/A
D21 LA17_CC_N SYNCFMC max17687_sync_clk LVCMOS25 #N/A
16 changes: 13 additions & 3 deletions projects/ad4630_fmc/zed/README.md
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Expand Up @@ -3,8 +3,9 @@

## Building the design

The design supports almost all the digital interface modes of AD4630-24, a new
bit stream should be generated each time when the targeted configuration changes.
The design supports almost all the digital interface modes of AD463x, AD403x
and adaq42xx a new bit stream should be generated each time when the targeted
configuration changes.

Default configuration: generic SPI mode for clocking, 2 lanes per channel, SDR
data capture and capture zone 2.
Expand All @@ -18,7 +19,16 @@ data capture and capture zone 2.
| CAPTURE_ZONE | 1 - negedge of BUSY / 2 - next posedge of CNV |
| DDR_EN | 0 - MISO runs on SDR / 1 - MISO runs on DDR |

**Example:** make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0
**Example:**
make CLK_MODE=0 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0
make CLK_MODE=0 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0
make CLK_MODE=0 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=0
make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0
make CLK_MODE=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0
make CLK_MODE=1 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=0
make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=1
make CLK_MODE=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=1
make CLK_MODE=1 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=1

## Documentation

Expand Down
9 changes: 8 additions & 1 deletion projects/ad4630_fmc/zed/system_constr.xdc
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###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

Expand All @@ -14,6 +14,13 @@ set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports ad463x_busy]
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad463x_cnv] ; ## D8 FMC_LA01_CC_P
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports ad463x_ext_clk] ; ## H4 FMC_CLK0_P

set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {adaq42xx_pgia_mux[0]}] ; ## G12 FMC-LA08_P
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports {adaq42xx_pgia_mux[1]}] ; ## G13 FMC-LA08_N

set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports max17687_rst] ; ## H13 FMC-LA07_P
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports max17687_en] ; ## H14 FMC-LA07_N
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports max17687_sync_clk] ; ## D21 FMC-LA17_N_CC

# external clock, that drives the CNV generator, must have a maximum 100 MHz frequency
create_clock -period 10.000 -name cnv_ext_clk [get_ports ad463x_ext_clk]

Expand Down
26 changes: 18 additions & 8 deletions projects/ad4630_fmc/zed/system_top.v
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -95,7 +95,13 @@ module system_top #(
input ad463x_ext_clk,
output ad463x_cnv,
input ad463x_busy,
inout ad463x_resetn
inout ad463x_resetn,

inout [ 1:0] adaq42xx_pgia_mux,

inout max17687_rst,
output max17687_en,
output max17687_sync_clk
);

// internal signals
Expand All @@ -114,7 +120,8 @@ module system_top #(

// instantiations

assign gpio_i[63:33] = 31'b0;
assign gpio_i[63:36] = 27'b0;
assign max17687_en = 1'b1;

ad_data_clk #(
.SINGLE_ENDED (1)
Expand All @@ -135,12 +142,14 @@ module system_top #(
.clk (ad463x_echo_sclk_s));

ad_iobuf #(
.DATA_WIDTH(1)
.DATA_WIDTH(4)
) i_ad463x_gpio_iobuf (
.dio_t(gpio_t[32]),
.dio_i(gpio_o[32]),
.dio_o(gpio_i[32]),
.dio_p(ad463x_resetn));
.dio_t(gpio_t[35:32]),
.dio_i(gpio_o[35:32]),
.dio_o(gpio_i[35:32]),
.dio_p ({max17687_rst, // 35
adaq42xx_pgia_mux, // 34:33
ad463x_resetn})); // 32

ad_iobuf #(
.DATA_WIDTH(32)
Expand Down Expand Up @@ -235,6 +244,7 @@ module system_top #(
.ad463x_busy (ad463x_busy),
.ad463x_cnv (ad463x_cnv),
.ad463x_ext_clk (ext_clk_s),
.max17687_sync_clk (max17687_sync_clk),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif));

Expand Down

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