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Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
analogdevicesinc · Apr 12, 2024 · 9b258f3 · 9b258f3
1 parent e224aa7
commit 9b258f3
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Showing 8 changed files with 32 additions and 53 deletions.
diff --git a/library/axi_pulsar_lvds/axi_pulsar_lvds.v b/library/axi_pulsar_lvds/axi_pulsar_lvds.v
@@ -36,7 +36,6 @@
 `timescale 1ns/100ps
 
 module axi_pulsar_lvds #(
-
   parameter ID = 0,
   parameter FPGA_TECHNOLOGY = 0,
   parameter FPGA_FAMILY = 0,
@@ -65,7 +64,7 @@ module axi_pulsar_lvds #(
   // dma interface
 
   output        adc_valid,
-  output [31:0] adc_data,
+  output [BITS_PER_SAMPLE-1:0] adc_data,
   input         adc_dovf,
 
   // axi interface

diff --git a/library/axi_pulsar_lvds/axi_pulsar_lvds_channel.v b/library/axi_pulsar_lvds/axi_pulsar_lvds_channel.v
@@ -53,7 +53,7 @@ module axi_pulsar_lvds_channel #(
 
   output        adc_enable,
   output        adc_valid,
-  output [31:0] adc_data,
+  output [BITS_PER_SAMPLE-1:0] adc_data,
 
   // error monitoring
 

diff --git a/library/axi_pulsar_lvds/axi_pulsar_lvds_ip.tcl b/library/axi_pulsar_lvds/axi_pulsar_lvds_ip.tcl
@@ -30,6 +30,16 @@ adi_ip_files axi_pulsar_lvds [list \
 
 adi_ip_properties axi_pulsar_lvds
 
+adi_add_bus "fifo_wr" "master" \
+        "analog.com:interface:fifo_wr_rtl:1.0" \
+        "analog.com:interface:fifo_wr:1.0" \
+        { \
+                {"adc_valid" "EN"} \
+                {"adc_data" "DATA"} \
+                {"adc_dovf" "OVERFLOW"} \
+        }
+adi_add_bus_clock "fifo_wr_clk" "fifo_wr"
+
 adi_init_bd_tcl
 adi_ip_bd axi_pulsar_lvds "bd/bd.tcl"
 

diff --git a/projects/pulsar_lvds_adc/Readme.md b/projects/pulsar_lvds_adc/Readme.md
@@ -13,4 +13,5 @@ Here are some pointers to help you:
 How to use over-writable parameters from the environment:
 ```
 hdl/projects/pulsar_lvds_adc/zed> make RESOLUTION_16_18N=0
-RESOLUTION_16_18N  - Defines the resolution of the ADC: 0 - 18 BITS, 1 - 16 BITS.
+RESOLUTION_16_18N  - Defines the resolution of the ADC: 0 - 18 BITS, 1 - 16 BITS.
+```
diff --git a/projects/pulsar_lvds_adc/common/pulsar_lvds_adc_bd.tcl b/projects/pulsar_lvds_adc/common/pulsar_lvds_adc_bd.tcl
@@ -9,8 +9,6 @@ puts "build parameters: RESOLUTION_16_18N: $RESOLUTION_16_18N"
 set ADC_DATA_WIDTH [expr {$RESOLUTION_16_18N == 1 ? 16 : 18}]
 set BITS_PER_SAMPLE [expr {$RESOLUTION_16_18N == 1 ? 16 : 32}]
 
-# ltc2387
-create_bd_port -dir I ref_clk
 create_bd_port -dir O sampling_clk
 create_bd_port -dir I dco_p
 create_bd_port -dir I dco_n
@@ -70,9 +68,7 @@ ad_connect d_p        axi_pulsar_lvds/d_p
 ad_connect d_n        axi_pulsar_lvds/d_n
 
 ad_connect reference_clkgen/clk_0    axi_pulsar_lvds_dma/fifo_wr_clk
-ad_connect axi_pulsar_lvds/adc_valid axi_pulsar_lvds_dma/fifo_wr_en
-ad_connect axi_pulsar_lvds/adc_data  axi_pulsar_lvds_dma/fifo_wr_din
-ad_connect axi_pulsar_lvds/adc_dovf  axi_pulsar_lvds_dma/fifo_wr_overflow
+ad_connect axi_pulsar_lvds/fifo_wr   axi_pulsar_lvds_dma/fifo_wr
 
 ad_connect cnv                    axi_pwm_gen/pwm_0
 ad_connect clk_gate               axi_pwm_gen/pwm_1
@@ -85,7 +81,8 @@ ad_connect sys_cpu_clk            axi_pwm_gen/s_axi_aclk
 ad_cpu_interconnect 0x44A00000 axi_pulsar_lvds
 ad_cpu_interconnect 0x44A30000 axi_pulsar_lvds_dma
 ad_cpu_interconnect 0x44A60000 axi_pwm_gen
-ad_cpu_interconnect 0x44a80000 reference_clkgen
+ad_cpu_interconnect 0x44A80000 reference_clkgen
+
 # interconnect (adc)
 
 ad_mem_hp2_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP2

diff --git a/projects/pulsar_lvds_adc/zed/ad7626_system_top.v b/projects/pulsar_lvds_adc/zed/ad7626_system_top.v
@@ -83,8 +83,6 @@ module system_top (
 
   input         otg_vbusoc,
 
-  input         ref_clk_p,
-  input         ref_clk_n,
   output        clk_p,
   output        clk_n,
   input         dco_p,
@@ -114,7 +112,6 @@ module system_top (
   wire [ 1:0] iic_mux_sda_o_s;
   wire        iic_mux_sda_t_s;
 
-  wire        clk_s;
   wire        cnv_s;
   wire        cnv;
   wire        clk_gate;
@@ -134,15 +131,6 @@ module system_top (
 
   // instantiations
 
-  ad_data_clk #(
-    .SINGLE_ENDED (0)
-  ) i_ref_clk (
-    .rst (1'b0),
-    .locked (),
-    .clk_in_p (ref_clk_p),
-    .clk_in_n (ref_clk_n),
-    .clk (clk_s));
-
   ODDR #(
     .DDR_CLK_EDGE ("SAME_EDGE")
   ) i_tx_clk_oddr (
@@ -244,7 +232,6 @@ module system_top (
     .iic_mux_sda_t (iic_mux_sda_t_s),
     .otg_vbusoc (otg_vbusoc),
     .spdif (spdif),
-    .ref_clk (clk_s),
     .sampling_clk (sampling_clk_s),
     .dco_p (dco_p),
     .dco_n (dco_n),

diff --git a/projects/pulsar_lvds_adc/zed/ad7960_system_top.v b/projects/pulsar_lvds_adc/zed/ad7960_system_top.v
@@ -83,8 +83,6 @@ module system_top (
 
   input         otg_vbusoc,
 
-  input         ref_clk_p,
-  input         ref_clk_n,
   output        clk_p,
   output        clk_n,
   input         dco_p,
@@ -113,7 +111,6 @@ module system_top (
   wire [ 1:0] iic_mux_sda_o_s;
   wire        iic_mux_sda_t_s;
 
-  wire        clk_s;
   wire        cnv_s;
   wire        cnv;
   wire        clk_gate;
@@ -135,15 +132,6 @@ module system_top (
 
   // instantiations
 
-  ad_data_clk #(
-    .SINGLE_ENDED (0)
-  ) i_ref_clk (
-    .rst (1'b0),
-    .locked (),
-    .clk_in_p (ref_clk_p),
-    .clk_in_n (ref_clk_n),
-    .clk (clk_s));
-
   ODDR #(
     .DDR_CLK_EDGE ("SAME_EDGE")
   ) i_tx_clk_oddr (
@@ -245,7 +233,6 @@ module system_top (
     .iic_mux_sda_t (iic_mux_sda_t_s),
     .otg_vbusoc (otg_vbusoc),
     .spdif (spdif),
-    .ref_clk (clk_s),
     .sampling_clk (sampling_clk_s),
     .dco_p (dco_p),
     .dco_n (dco_n),

diff --git a/projects/pulsar_lvds_adc/zed/system_constr.tcl b/projects/pulsar_lvds_adc/zed/system_constr.tcl
@@ -9,39 +9,37 @@ if {![info exists RESOLUTION_16_18N]} {
 
 # clocks
 
-set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports ref_clk_p]
-set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports ref_clk_n]
-set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25} [get_ports clk_p]
-set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25} [get_ports clk_n]
+set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25} [get_ports clk_p];                         ## G06 FMC_LPC_LA00_CC_P
+set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25} [get_ports clk_n];                         ## G07 FMC_LPC_LA00_CC_N
 
 # cnv
 
-set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25} [get_ports cnv_p]
-set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25} [get_ports cnv_n]
+set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25} [get_ports cnv_p];                         ## D08 FMC_LPC_LA01_CC_P
+set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25} [get_ports cnv_n];                         ## D09 FMC_LPC_LA01_CC_N
 
 # dco, da
 
-set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports dco_p]
-set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports dco_n]
-set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports d_p]
-set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports d_n]
+set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports dco_p];              ## H04 FMC_LPC_CLK0_M2C_P
+set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports dco_n];              ## H05 FMC_LPC_CLK0_M2C_N
+set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports d_p];                ## H07 FMC_LPC_LA02_P
+set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports d_n];                ## H08 FMC_LPC_LA02_N
 
 # control signals
-set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports en0_fmc]
-set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports en1_fmc]
+set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports en0_fmc];                       ## G09 FMC_LPC_LA03_P
+set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports en1_fmc];                       ## G10 FMC_LPC_LA03_N
 
 switch $RESOLUTION_16_18N {
   0 {
 
-    set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports en2_fmc]
-    set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports en3_fmc]
+    set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports en2_fmc];                   ## H10 FMC_LPC_LA04_P
+    set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports en3_fmc];                   ## H11 FMC_LPC_LA04_N
   }
   1 {
 
-    set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports fpga_pll_cnv_p]
-    set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports fpga_pll_cnv_n]
+    set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports fpga_pll_cnv_p]; ## H10 FMC_LPC_LA04_P
+    set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports fpga_pll_cnv_n]; ## H11 FMC_LPC_LA04_N
 
-    set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports pll_sync_fmc]
+    set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports pll_sync_fmc];              ## D11 FMC_LPC_LA05_P
   }
 }