projects/pulsar_lvds_adc: GPIO modification

Updated GPIOs and system_constr.tcl. Updated Copyright. Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
analogdevicesinc · Feb 21, 2024 · aa6832b · aa6832b
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diff --git a/library/axi_pulsar_lvds/Makefile b/library/axi_pulsar_lvds/Makefile
@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################

diff --git a/library/axi_pulsar_lvds/axi_pulsar_lvds.v b/library/axi_pulsar_lvds/axi_pulsar_lvds.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -158,7 +158,7 @@ module axi_pulsar_lvds #(
     .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY),
     .IODELAY_CTRL (IODELAY_CTRL),
     .ADC_DATA_WIDTH (ADC_DATA_WIDTH)
-    
+
   ) axi_pulsar_lvds_if_inst (
     .up_clk(up_clk),
     .up_dld(up_dld_s),

diff --git a/library/axi_pulsar_lvds/axi_pulsar_lvds_channel.v b/library/axi_pulsar_lvds/axi_pulsar_lvds_channel.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are

diff --git a/library/axi_pulsar_lvds/axi_pulsar_lvds_if.v b/library/axi_pulsar_lvds/axi_pulsar_lvds_if.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are

diff --git a/library/axi_pulsar_lvds/axi_pulsar_lvds_ip.tcl b/library/axi_pulsar_lvds/axi_pulsar_lvds_ip.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 

diff --git a/projects/pulsar_lvds_adc/Makefile b/projects/pulsar_lvds_adc/Makefile
@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################

diff --git a/projects/pulsar_lvds_adc/Readme.md b/projects/pulsar_lvds_adc/Readme.md
@@ -1,4 +1,4 @@
-# CN0577 HDL Project
+# PULSAR_LVDS_ADC HDL Project
 
 Here are some pointers to help you:
   * [EVAL-AD7626 board Product Page ](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD7626.html)
@@ -9,5 +9,8 @@ Here are some pointers to help you:
   * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/circuits-from-the-lab/cn0577/hdl
   * Project Doc: https://wiki.analog.com/resources/eval/user-guides/circuits-from-the-lab/cn0577
   * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ltc2387
-
 
+How to use over-writable parameters from the environment:
+```
+hdl/projects/pulsar_lvds_adc/zed> make RESOLUTION_16_18N=0
+RESOLUTION_16_18N  - Defines the resolution of the ADC: 0 - 18 BITS, 1 - 16 BITS.
diff --git a/projects/pulsar_lvds_adc/common/pulsar_lvds_adc_bd.tcl b/projects/pulsar_lvds_adc/common/pulsar_lvds_adc_bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -56,7 +56,7 @@ ad_ip_parameter reference_clkgen CONFIG.VCO_MUL 10
 ad_ip_parameter reference_clkgen CONFIG.CLK0_DIV 6
 #ad_ip_parameter reference_clkgen CONFIG.CLK1_DIV 4
 
-ad_connect reference_clkgen/clk   $sys_cpu_clk             
+ad_connect reference_clkgen/clk   $sys_cpu_clk
 ad_connect reference_clkgen/clk_0 sampling_clk
 ad_connect reference_clkgen/clk_0 axi_pulsar_lvds/ref_clk
 

diff --git a/projects/pulsar_lvds_adc/zed/Makefile b/projects/pulsar_lvds_adc/zed/Makefile
@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################

diff --git a/projects/pulsar_lvds_adc/zed/ad7626_system_top.v b/projects/pulsar_lvds_adc/zed/ad7626_system_top.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -95,7 +95,7 @@ module system_top (
   output                  cnv_p,
   output                  cnv_n,
   inout                   en0_fmc,
-  inout                   en1_fmc,  
+  inout                   en1_fmc,
   inout                   fpga_pll_cnv_p,
   inout                   fpga_pll_cnv_n,
   inout                   pll_sync_fmc
@@ -124,14 +124,12 @@ module system_top (
   assign gpio_i[63:36] = gpio_o[63:36];
 
   ad_iobuf #(
-    .DATA_WIDTH(4)
+    .DATA_WIDTH(2)
   ) i_iobuf (
-    .dio_t(gpio_t[35:32]),
-    .dio_i(gpio_o[35:32]),
-    .dio_o(gpio_i[35:32]),
-    .dio_p({en3_fmc,      // 89
-            en2_fmc,      // 88
-            en1_fmc,      // 87
+    .dio_t(gpio_t[33:32]),
+    .dio_i(gpio_o[33:32]),
+    .dio_o(gpio_i[33:32]),
+    .dio_p({en1_fmc,      // 87
             en0_fmc}));   // 86
 
   // instantiations

diff --git a/projects/pulsar_lvds_adc/zed/ad7960_system_top.v b/projects/pulsar_lvds_adc/zed/ad7960_system_top.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are

diff --git a/projects/pulsar_lvds_adc/zed/system_bd.tcl b/projects/pulsar_lvds_adc/zed/system_bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 

diff --git a/projects/pulsar_lvds_adc/zed/system_constr.tcl b/projects/pulsar_lvds_adc/zed/system_constr.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -25,11 +25,11 @@ set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25} [get_ports cnv_n]
 
 set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports dco_p]
 set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports dco_n]
-set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports d_p] 
+set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports d_p]
 set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports d_n]
 
-# control signals 
-set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports en0_fmc]   
+# control signals
+set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports en0_fmc]
 set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports en1_fmc]
 
 switch $RESOLUTION_16_18N {
@@ -38,14 +38,14 @@ switch $RESOLUTION_16_18N {
     set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports en2_fmc]
     set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports en3_fmc]
   }
-  1 { 
-    
-    set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports fpga_pll_cnv_p]
-    set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports fpga_pll_cnv_n]
+  1 {
+
+    set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports fpga_pll_cnv_p]
+    set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports fpga_pll_cnv_n]
 
     set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports pll_sync_fmc]
   }
-}  
+}
 
 # 166.66 MHz clock
 
@@ -61,8 +61,5 @@ set input_ports         d_p;      # List of input ports
 # Input Delay Constraint
 set_input_delay -clock $input_clock -max [expr $input_clock_period - $dv_bre] [get_ports $input_ports];
 set_input_delay -clock $input_clock -min $dv_are                              [get_ports $input_ports];
-
-# Report Timing Template
-# report_timing -from [get_ports $input_ports] -max_paths 20 -nworst 1 -delay_type min_max -name src_sync_cntr_rise_in  -file src_sync_cntr_rise_in.txt;		  
 
 set_clock_uncertainty -setup -from [get_clocks out_clock] -to [get_clocks dco] 7.000
diff --git a/projects/pulsar_lvds_adc/zed/system_project.tcl b/projects/pulsar_lvds_adc/zed/system_project.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -8,10 +8,9 @@ source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
-# DEV_CONFIG - The device which will be used
 # RESOLUTION_16_18N - The resolution of the ADC
 # LEGEND: 18 BITS RESOLUTION AD7960 - 0
-#         16 BITS RESOLUTION AD7626 - 1 
+#         16 BITS RESOLUTION AD7626 - 1
 
 set RESOLUTION_16_18N [get_env_param RESOLUTION_16_18N 0]
 
@@ -34,6 +33,6 @@ adi_project_files pulsar_lvds_adc_zed [list \
     adi_project_files pulsar_lvds_adc_zed [list \
       "ad7626_system_top.v" ]
   }
-} 
+}
 
 adi_project_run pulsar_lvds_adc_zed