ad405x: Update coraz7s constraints

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
analogdevicesinc · Oct 17, 2023 · cc25bbe · cc25bbe
1 parent e0bcd9c
commit cc25bbe
Show file tree

Hide file tree

Showing 2 changed files with 7 additions and 6 deletions.
diff --git a/projects/ad405x_i3c_ardz/coraz7s/system_constr.xdc b/projects/ad405x_i3c_ardz/coraz7s/system_constr.xdc
@@ -3,8 +3,12 @@
 # Ultrascale devices could use IOB_TRI_REG.
 # Since IOB_TRI_REG is not available in the zynq7000 the tristate flip-flop is placed in the device fabric.
 # Valid IOSTANDARD for the I3C bus are: LVCMOS12, LVCMOS18, and LVCMOS33
-set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 PULLTYPE PULLUP IOB FALSE DRIVE 12 IBUF_LOW_PWR FALSE SLEW FAST} [get_ports i3c_controller_0_sda] ; ##  PMOD JA [1]
-set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 PULLTYPE PULLUP IOB FALSE DRIVE 12 SLEW FAST} [get_ports i3c_controller_0_scl] ; ##  PMOD JA [0]
+# I3C at SDA and SCL ports, no PULLUP, has external PULLUP in the board.
+set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33 PULLTYPE {} IOB FALSE DRIVE 12 SLEW FAST} [get_ports i3c_controller_0_scl] ; ##  CK_SCL
+set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33 PULLTYPE {} IOB FALSE DRIVE 12 IBUF_LOW_PWR FALSE SLEW FAST} [get_ports i3c_controller_0_sda] ; ##  CK_SDA
+# I3C at IO13 and IO12 ports, enable external PULLUP in the eval board for the SDA lane.
+#set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33 PULLTYPE {} IOB FALSE DRIVE 12 SLEW FAST} [get_ports i3c_controller_0_scl] ; ## CK_IO4
+#set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33 PULLTYPE {} IOB FALSE DRIVE 12 IBUF_LOW_PWR FALSE SLEW FAST} [get_ports i3c_controller_0_sda] ; ## CK_IO3
 
 # clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk
 set i3c_clk clk_fpga_0
@@ -20,9 +24,6 @@ set_multicycle_path -from [get_clocks clk_fpga_0] -to [get_ports i3c_controller_
 set_multicycle_path -from [get_clocks clk_fpga_0] -to [get_ports i3c_controller_0_scl] -setup 2
 set_multicycle_path -from [get_clocks clk_fpga_0] -to [get_ports i3c_controller_0_scl] -hold 1
 
-set_multicycle_path -from [get_clocks clk_1] -to [get_clocks $i3c_clk] -setup 4
-set_multicycle_path -from [get_clocks clk_1] -to [get_clocks $i3c_clk] -hold  3
-
 # Notes
 # tcr/tcf rising/fall time for SCL is 150e06 * 1 / fSCL, at fSCL = 12.5 MHz => 12ns, at fSCL = 6.25 MHz, 24ns.
 # and t_SCO has a minimum/default value of 8ns and max of 12 ns

diff --git a/projects/common/coraz7s/coraz7s_system_constr.xdc b/projects/common/coraz7s/coraz7s_system_constr.xdc
@@ -5,7 +5,7 @@
 
 # constraints
 
-# gpio 
+# gpio
 
 set_property  -dict {PACKAGE_PIN  D20   IOSTANDARD LVCMOS33} [get_ports btn[0]]       ; ## BTN0
 set_property  -dict {PACKAGE_PIN  D19   IOSTANDARD LVCMOS33} [get_ports btn[1]]       ; ## BTN1
-Original file line number
+Diff line change
@@ Expand Up / @@ -5,7 +5,7 @@ @@
     # constraints
-    # gpio
+    # gpio
     set_property  -dict {PACKAGE_PIN  D20   IOSTANDARD LVCMOS33} [get_ports btn[0]]       ; ## BTN0
     set_property  -dict {PACKAGE_PIN  D19   IOSTANDARD LVCMOS33} [get_ports btn[1]]       ; ## BTN1
@@ Expand Down @@