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12 changes: 6 additions & 6 deletions library/axi_ad9144/index.html
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<span id="axi-ad9144"></span><h1>AXI AD9144 (OBSOLETE)<a class="headerlink" href="#axi-ad9144-obsolete" title="Permalink to this heading">#</a></h1>
<div class="admonition warning">
<p class="admonition-title">Warning</p>
<p>This IP is was discontinued, limited support available. Last release for this
IP is <code class="docutils literal notranslate"><span class="pre">hdl_2019_r2</span></code> and can be found on our HDL repository, on the branch
with the same name.</p>
<p>The support for <a class="icon git reference external" href="https://github.com/analogdevicesinc/hdl/tree/hdl_2019_r2/library/axi_ad9144">AXI AD9144</a>
has been discontinued, the latest tested release being <code class="docutils literal notranslate"><span class="pre">hdl_2019_r2</span></code>.
This page is for legacy purposes only.</p>
</div>
<p>The <a class="icon git reference external" href="https://github.com/analogdevicesinc/hdl/tree/hdl_2019_r2/library/axi_ad9144">AXI AD9144</a> IP core can be used
to interface the <a class="icon adi reference external" href="https://www.analog.com/AD9144">AD9144</a> DAC. An AXI Memory Map interface is used for
configuration. Data is sent in a format that can be transmitted by Xilinx’s
JESD IP. More about the generic framework interfacing DACs, can be read
in <a class="reference internal" href="../../user_guide/ip_cores/axi_adc/index.html#axi-adc"><span class="std std-ref">Generic AXI ADC</span></a>.</p>
configuration. Data is sent in a format that can be transmitted by AMD Xilinx’s
JESD IP.</p>
<p>More about the generic framework interfacing DACs, can be read in <a class="reference internal" href="../../user_guide/ip_cores/axi_adc/index.html#axi-adc"><span class="std std-ref">Generic AXI ADC</span></a>.</p>
<section id="features">
<h2>Features<a class="headerlink" href="#features" title="Permalink to this heading">#</a></h2>
<ul class="simple">
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9 changes: 5 additions & 4 deletions library/axi_ad9371/index.html
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<span id="axi-ad9371"></span><h1>AXI AD9371 (OBSOLETE)<a class="headerlink" href="#axi-ad9371-obsolete" title="Permalink to this heading">#</a></h1>
<div class="admonition warning">
<p class="admonition-title">Warning</p>
<p>This IP is was discontinued, limited support available. Last release for this
IP is <code class="docutils literal notranslate"><span class="pre">hdl_2019_r2</span></code> and can be found on our HDL repository, on the branch
with the same name.</p>
<p>The support for <a class="icon git reference external" href="https://github.com/analogdevicesinc/hdl/tree/hdl_2019_r2/library/axi_ad9371">AXI AD9371</a>
has been discontinued, the latest tested release being <code class="docutils literal notranslate"><span class="pre">hdl_2019_r2</span></code>.
This page is for legacy purposes only.</p>
</div>
<div class="admonition note">
<p class="admonition-title">Note</p>
Expand All @@ -341,7 +341,8 @@
<p>The <a class="icon git reference external" href="https://github.com/analogdevicesinc/hdl/tree/hdl_2019_r2/library/axi_ad9371">AXI AD9371</a> IP core can be used
to interface the <a class="icon adi reference external" href="https://www.analog.com/AD9371">AD9371</a> device. An AXI Memory Map interface is used for
configuration. Data is sent in a format that can be transmitted by Xilinx’s
JESD IP. More about the generic framework interfacing ADCs, that contains the
JESD IP.</p>
<p>More about the generic framework interfacing ADCs and DACs, that contains the
<code class="docutils literal notranslate"><span class="pre">up_dac_channel</span></code>, <code class="docutils literal notranslate"><span class="pre">up_adc_channel</span></code> and <code class="docutils literal notranslate"><span class="pre">up_dac_common</span> <span class="pre">modules</span></code>,
<code class="docutils literal notranslate"><span class="pre">up_adc_common</span> <span class="pre">modules</span></code> can be read in <a class="reference internal" href="../../user_guide/ip_cores/axi_dac/index.html#axi-dac"><span class="std std-ref">Generic AXI DAC</span></a> and <a class="reference internal" href="../../user_guide/ip_cores/axi_adc/index.html#axi-adc"><span class="std std-ref">Generic AXI ADC</span></a>.</p>
<section id="features">
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<div class="admonition warning">
<p class="admonition-title">Warning</p>
<p>The support for <a class="icon git reference external" href="https://github.com/analogdevicesinc/hdl/tree/hdl_2016_r1/library/axi_ad9643">AXI AD9643</a> IP
has been discontinued, the latest tested release being hdl_2016_r1.
has been discontinued, the latest tested release being <code class="docutils literal notranslate"><span class="pre">hdl_2016_r1</span></code>.
This page is for legacy purposes only.</p>
</div>
<p>The <a class="icon git reference external" href="https://github.com/analogdevicesinc/hdl/tree/hdl_2016_r1/library/axi_ad9643">AXI AD9643</a> IP core was used
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</div><p>The <a class="icon git reference external" href="https://github.com/analogdevicesinc/hdl/tree/main/library/axi_ad9671">AXI AD9671</a> IP core
</div><div class="admonition warning">
<p class="admonition-title">Warning</p>
<p>The support for <a class="icon git reference external" href="https://github.com/analogdevicesinc/hdl/tree/hdl_2022_r2/library/axi_ad9671">AXI AD9671</a>
has been discontinued.
This page is kept for legacy purposes only.</p>
</div>
<p>The <a class="icon git reference external" href="https://github.com/analogdevicesinc/hdl/tree/hdl_2022_r2/library/axi_ad9671">AXI AD9671</a> IP core
can be used to interface the <a class="icon adi reference external" href="https://www.analog.com/AD9671">AD9671</a> Octal Ultrasound AFE with digital
demodulator.
An AXI Memory Map interface is used for configuration.
Data is received from Xilinx JESD IP.</p>
Data is received from AMD Xilinx JESD IP.</p>
<p>More about the generic framework interfacing ADCs can be read in <a class="reference internal" href="../../user_guide/ip_cores/axi_adc/index.html#axi-adc"><span class="std std-ref">Generic AXI ADC</span></a>.</p>
<section id="features">
<h2>Features<a class="headerlink" href="#features" title="Permalink to this heading">#</a></h2>
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<p>The goal of this tutorial is to present the process of adding
<a class="reference internal" href="index.html#spi-engine"><span class="std std-ref">SPI Engine</span></a> support for an ADI precision converter or family of converters
using a few simple steps.
The target carrier is the Digilent Cora-z7s board using a PMOD connector.</p>
The target carrier is the Digilent Cora Z7S board using a PMOD connector.</p>
<section id="evaluating-the-target-device">
<h2>Evaluating the target device<a class="headerlink" href="#evaluating-the-target-device" title="Permalink to this heading">#</a></h2>
<p>The aim of this project is to provide support for a family of ADCs which come in
Expand All @@ -345,7 +345,7 @@ <h2>Evaluating the target device<a class="headerlink" href="#evaluating-the-targ
in their performance. The table below offers a comparison between the timing
parameters of the SPI interface for these devices. Using this table we can see
how much they have in common and where the key differences are. All the values
are for 3.3V VIO since the Cora-z7s is only 3.3V capable.</p>
are for 3.3V VIO since the Cora Z7S is only 3.3V capable.</p>
<div class="table-wrapper docutils container">
<table class="docutils align-default">
<thead>
Expand Down Expand Up @@ -574,7 +574,7 @@ <h2>AD7984 Timing diagram<a class="headerlink" href="#ad7984-timing-diagram" tit
<span class="nv">750</span><span class="w"> </span>ns<span class="w"> </span>T_CYC
<span class="nv">500</span><span class="w"> </span>ns<span class="w"> </span>T_CONV
<span class="nv">250</span><span class="w"> </span>ns<span class="w"> </span>T_ACQ
<span class="nv">12</span><span class="w"> </span>ns<span class="w"> </span>T_SCLK<span class="w"> </span>@<span class="w"> </span><span class="o">&gt;</span><span class="mi">3</span>V<span class="w"> </span>VIO<span class="w"> </span><span class="k">(</span><span class="nv">cora</span><span class="w"> </span>pmod<span class="w"> </span>is<span class="w"> </span><span class="mi">3</span>V3<span class="k">)</span>
<span class="nv">12</span><span class="w"> </span>ns<span class="w"> </span>T_SCLK<span class="w"> </span>@<span class="w"> </span><span class="o">&gt;</span><span class="mi">3</span>V<span class="w"> </span>VIO<span class="w"> </span><span class="k">(</span><span class="nv">Cora</span><span class="w"> </span>PMOD<span class="w"> </span>is<span class="w"> </span><span class="mi">3</span>V3<span class="k">)</span>
</pre></div>
</div>
<section id="sample-rate-control">
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