projects/ad9265_fmc: Solved the requested changes

Updated the HDL project and the documentation. Reverted the changes used for debugging.

Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>

docs/projects/ad9265_fmc/index.rst

@@ -58,25 +58,20 @@ Block diagram
 Clock scheme
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-There are 3 ways to configure the clock source for :adi:`AD9265` (some 
-modification maybe necessary).
+There are 3 ways to configure the clock source for :adi:`AD9265`:
 
 - External passive clock (default)
 - Optional active clock path using the :adi:`AD9517`
 - Optional oscillator
 
 For more details, check :adi:`AD9265` schematic.
 
-
 CPU/Memory interconnects addresses
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 The addresses are dependent on the architecture of the FPGA, having an offset
 added to the base address from HDL (see more at :ref:`architecture`).
 
-Depending on the values of parameters $INTF_CFG, $ADI_PHY_SEL and $TDD_SUPPORT,
-some IPs are instatiated and some are not.
-
 Check-out the table below to find out the conditions.
 
 ==================== =============== 
@@ -89,9 +84,6 @@ axi_ad9265_dma       0x44A30000
 SPI connections
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-THESE ARE JUST EXAMPLES!!!
-USE WHICHEVER FITS BEST YOUR CASE
-
 .. list-table::
    :widths: 25 25 25 25
    :header-rows: 1
@@ -104,20 +96,12 @@ USE WHICHEVER FITS BEST YOUR CASE
      - SPI 0
      - AD9517
      - 1
-   * - PS
-     - SPI 1
-     - AD0000
-     - 0
 
 Interrupts
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 Below are the Programmable Logic interrupts used in this project.
 
-You have many ways of writing this table: as a list-table or really to draw
-it. Take a look in the .rst of this page to see how they're written and
-which suits best your case.
-
 .. list-table::
    :widths: 30 10 15 15
    :header-rows: 1
@@ -141,8 +125,8 @@ the source you must
 `clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
 the HDL repository.
 
-Then go to the project location(**projects/ad9265_fmc/carrier**) and run the make command by
-typing in your command prompt(this example :adi:`ZC706``):
+Then go to the project location (**projects/ad9265_fmc/carrier**) and run the make command by
+typing in your command prompt(this example :xilinx:`ZC706`):
 
 **Linux/Cygwin/WSL**
 
@@ -174,7 +158,7 @@ Hardware related
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 -  Product datasheets: :adi:`AD9265`
--  :dokuwiki:`Evaluating AD9434, user guide <resources/eval/ad9265-fmc-125ebz>`
+-  :dokuwiki:`Evaluating AD9265, user guide <resources/eval/ad9265-fmc-125ebz>`
 
 HDL related
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -189,7 +173,7 @@ HDL related
      - Source code link
      - Documentation link
    * - AXI_AD9265
-     - :git-hdl:`library/axi_ad9434 <library/axi_ad9265>`
+     - :git-hdl:`library/axi_ad9265 <library/axi_ad9265>`
      - ---
    * - AXI_DMAC
      - :git-hdl:`library/axi_dmac <library/axi_dmac>`
@@ -198,7 +182,7 @@ HDL related
      - :git-hdl:`library/axi_clkgen <library/axi_clkgen>`
      - :dokuwiki:`[Wiki] <resources/fpga/docs/axi_clkgen>`
    * - AXI_HDMI_TX
-     - :git-hdl:`library/axi_hdmi_tx <library/axi_ad9434>`
+     - :git-hdl:`library/axi_hdmi_tx <library/axi_hdmi_tx>`
      - :dokuwiki:`[Wiki] <resources/fpga/docs/axi_hdmi_tx>`
    * - AXI_SPDIF_TX
      - :git-hdl:`library/axi_spdif_tx <library/axi_spdif_tx>`

projects/ad9265_fmc/common/ad9265_fmc.txt

@@ -0,0 +1,32 @@
+FMC_pin     FMC_port            Schematic_name       System_top_name     IOSTANDARD     Termination
+
+# ad9265
+
+H4          CLK0_M2C_P          DCO+_GLOBAL          adc_clk_in_p        LVDS_25        DIFF_TERM TRUE
+H5          CLK0_M2C_N          DCO-_GLOBAL          adc_clk_in_n        LVDS_25        DIFF_TERM TRUE
+
+D14         LA09_P              D0/1+                adc_data_in_p[0]    LVDS_25        DIFF_TERM TRUE
+D15         LA09_N              D0/1-                adc_data_in_n[0]    LVDS_25        DIFF_TERM TRUE
+C10         LA06_P              D2/3+                adc_data_in_p[1]    LVDS_25        DIFF_TERM TRUE
+C11         LA06_N              D2/3-                adc_data_in_n[1]    LVDS_25        DIFF_TERM TRUE
+H13         LA07_P              D4/5+                adc_data_in_p[2]    LVDS_25        DIFF_TERM TRUE
+H14         LA07_N              D4/5-                adc_data_in_n[2]    LVDS_25        DIFF_TERM TRUE
+G12         LA08_P              D6/7+                adc_data_in_p[3]    LVDS_25        DIFF_TERM TRUE
+G13         LA08_N              D6/7-                adc_data_in_n[3]    LVDS_25        DIFF_TERM TRUE
+H10         LA04_P              D8/9+                adc_data_in_p[4]    LVDS_25        DIFF_TERM TRUE
+H11         LA04_N              D8/9-                adc_data_in_n[4]    LVDS_25        DIFF_TERM TRUE
+D11         LA05_P              D10/11+              adc_data_in_p[5]    LVDS_25        DIFF_TERM TRUE
+D12         LA05_N              D10/11-              adc_data_in_n[5]    LVDS_25        DIFF_TERM TRUE
+H7          LA02_P              D12/13+              adc_data_in_p[6]    LVDS_25        DIFF_TERM TRUE
+H8          LA02_N              D12/13-              adc_data_in_n[6]    LVDS_25        DIFF_TERM TRUE
+G9          LA03_P              D14/15+              adc_data_in_p[7]    LVDS_25        DIFF_TERM TRUE
+G10         LA03_N              D14/15-              adc_data_in_n[7]    LVDS_25        DIFF_TERM TRUE
+D8          LA01_CC_P           OR+                  adc_data_or_p       LVDS_25        DIFF_TERM TRUE
+D9          LA01_CC_N           OR-                  adc_data_or_n       LVDS_25        DIFF_TERM TRUE
+
+# spi
+
+G36         LA33_P              AD9517_CSB           spi_csn_clk         LVCMOS25       #N/A
+G37         LA33_N              CSB                  spi_csn_adc         LVCMOS25       #N/A
+H37         LA32_P              SDIO                 spi_sdio            LVCMOS25       #N/A
+H38         LA32_N              SCLK                 spi_clk             LVCMOS25       #N/A

projects/ad9265_fmc/zed/Makefile

@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################

projects/ad9265_fmc/zed/system_bd.tcl

@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 

projects/ad9265_fmc/zed/system_constr.xdc

@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -36,4 +36,4 @@ set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports spi_clk]
 
 # clocks
 
-create_clock -name adc_clk      -period 3.33 [get_ports adc_clk_in_p]
+create_clock -name adc_clk      -period 3.33             [get_ports adc_clk_in_p]                   ;

projects/ad9265_fmc/zed/system_project.tcl

@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 

projects/ad9265_fmc/zed/system_top.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -98,10 +98,9 @@ module system_top (
 
   // internal signals
 
-  wire    [ 1:0]  spi_csn; // not sure if it's necessearry 
   wire            spi_miso;
   wire            spi_mosi;
-  
+
   wire    [63:0]  gpio_i;
   wire    [63:0]  gpio_o;
   wire    [63:0]  gpio_t;
@@ -111,7 +110,7 @@ module system_top (
   wire    [ 1:0]  iic_mux_sda_i_s;
   wire    [ 1:0]  iic_mux_sda_o_s;
   wire            iic_mux_sda_t_s;
-  
+
   wire    [ 2:0]  spi0_csn;
   wire            spi0_clk;
   wire            spi0_mosi;