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analogdevicesinc · Jul 22, 2024 · e297f66 · e297f66
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diff --git a/_images/ad4134_hdl.svg b/_images/ad4134_hdl.svg
diff --git a/_images/cn0561_hdl.svg b/_images/cn0561_hdl.svg
diff --git a/projects/ad4134_fmc/index.html b/projects/ad4134_fmc/index.html
@@ -349,7 +349,7 @@ <h2>Block design<a class="headerlink" href="#block-design" title="Permalink to t
 FPGA. The device sends data on the 4 DIN bits.</p>
 <section id="block-diagram">
 <h3>Block diagram<a class="headerlink" href="#block-diagram" title="Permalink to this heading">#</a></h3>
-<p>The data path and clock domains are depicted in the below diagrams:</p>
+<p>The data path and clock domains are depicted in the below diagram:</p>
 <a class="reference internal image-reference" href="../../_images/ad4134_hdl.svg"><img alt="AD4134-FMC/ZED block diagram" class="align-center" src="../../_images/ad4134_hdl.svg" width="800" /></a>
 </section>
 <section id="jumper-setup">

diff --git a/projects/cn0561/index.html b/projects/cn0561/index.html
@@ -324,7 +324,7 @@ <h2>Overview<a class="headerlink" href="#overview" title="Permalink to this head
 board; to acquire data from the ADC device, supporting continuous data
 capture at maximum 1.5 MSPS data rate. However, due to a hardware limitation,
 the Cora-Z7s variant will only support a maximum data clock of 24MHz,
-in contrast with 48MHz supported on the Zedboard.</p>
+in contrast with 50MHz supported on the Zedboard.</p>
 </section>
 <section id="supported-boards">
 <h2>Supported boards<a class="headerlink" href="#supported-boards" title="Permalink to this heading">#</a></h2>

diff --git a/searchindex.js b/searchindex.js