FIX: qspi_sel connected properly

Changed some parts of the documentation.
Inserted EVAL-AD3552R documentation with some more info

Signed-off-by: <carlos.souza@analog.com>

docs/library/axi_ad3552r/index.rst

@@ -6,27 +6,32 @@ AXI AD35XXR
 .. hdl-component-diagram::
   :path: library/axi_ad35xxr
 
-The :git-hdl:`AXI AD3552R <library/axi_ad35xxr>` IP core can be used to
-interface the :adi:`AD3552R`, a low drift, ultra-fast, 16-bit accuracy, current 
-output digital-to-analog converter (DAC) that can be configured in multiple 
-voltage span ranges. It also supports :adi:`AD3542R`, a low drift, dual channel, 
-ultra-fast, 12-/16-bit accuracy, voltage output digital-to-analog converter 
-(DAC) that can be configured in multiple voltage span ranges.
+The :git-hdl:`AXI AD3552R <dev_ad3542r:library/axi_ad35xxr>` IP core can be used to
+interface the :adi:`AD3552R`, :adi:`AD3551R`, :adi:`AD3542R`, and
+:adi:`AD3541R`. :adi:`AD3552R` is a low drift, dual channel, ultra-fast, 
+16-bit accuracy, current output digital-to-analog converter (DAC) that can be 
+configured in multiple voltage span ranges, the :adi:`AD3551R` is the single 
+channel part. :adi:`AD3542R` is is a low drift, dual channel, ultra-fast, 
+12-/16-bit accuracy, voltage output digital-to-analog converter (DAC) that 
+can be configured in multiple voltage span ranges, the :adi:`AD3541R` is the
+single channel part.
+
 
 Features
 --------------------------------------------------------------------------------
 
-* AXI-based configuration
-* Vivado compatible
-* 8b register read/write SDR/DDR
-* 16b register read/write SDR/DDR
-* data stream SDR/DDR ( clk_in/8 or clk_in/4 update rate)
-* selectable input source: DMA/ADC/TEST_RAMP
-* data out clock(SCLK) has clk_in/2 frequency for both configuration and streaming
-  mode
-* the IP reference clock (clk_in) can have a maximum frequency of 132MHz
-* the IP has multiple device synchronization capability when the DMA is set
-  as an input data source
+* AXI-based configuration;
+* Vivado compatible;
+* 8b register read/write SDR/DDR;
+* 16b register read/write SDR/DDR;
+* Data stream SDR/DDR ( clk_in/8 or clk_in/4 update rate);
+* Selectable input source: DMA/ADC/TEST_RAMP;
+* Data out clock(SCLK) has clk_in/2 frequency for both configuration and streaming
+  mode;
+* The IP reference clock (clk_in) can have a maximum frequency of 132MHz;
+* The IP has multiple device synchronization capability when the DMA is set
+  as an input data source.
+
 
 Files
 --------------------------------------------------------------------------------
@@ -101,9 +106,9 @@ Interface
    * - valid_in_dma_sec
      - Valid from a secondary DMAC if synchronization is needed.
    * - external_sync
-     - External synchronization flag from another ad35xxr IP.
+     - External synchronization flag from another axi_ad35xxr IP.
    * - sync_ext_device
-     - Start_sync external device to another ad35xxr IP.
+     - Start_sync external device to another _axi_ad35xxr IP.
    * - dac_sclk
      - Serial clock.
    * - dac_csn
@@ -115,7 +120,8 @@ Interface
    * - sdio_t
      - I/O buffer control signal.
    * - qspi_sel
-     -  QSPI Mode Enable. High level enables quad SPI interface mode.
+     -  QSPI Mode Enable. High level enables quad SPI interface mode 
+        (ad3552r and ad3551r).
    * - s_axi
      - Standard AXI Slave Memory Map interface.
 
@@ -130,13 +136,16 @@ Detailed Description
 
 The top module instantiates:
 
-* The ad35xxr interface module
-* The ad35xxr core module
+* The axi_ad35xxr interface module
+* The axi_ad35xxr core module
 * The AXI handling interface
 
 The axi_ad35xxr_if has the state machine that controls the SPI interface,
 which can be Single SPI (Classic), Dual SPI, and Quad SPI.
-The axi_ad35xxr_core module instantiates 2 ad35xxr channel modules.
+The axi_ad35xxr_core module instantiates 2 ad35xxr channel modules even for
+the ad35x1r cases. For the single channel and 12 bit accuracy cases, consider
+the 16 LSBs -- The 4 LSBs of this word are 0's for the 12-bit accuracy.
+
 
 Register Map
 --------------------------------------------------------------------------------
@@ -199,6 +208,8 @@ References
 * HDL IP core at :git-hdl:`dev_ad3542r:library/axi_ad35xxr`
 * HDL project at :git-hdl:`dev_ad3542r:projects/ad35xxr_evb`
 * :adi:`AD3552R`
+* :adi:`AD3551R`
 * :adi:`AD3542R`
+* :adi:`AD3541R`
 * :xilinx:`Zynq-7000 SoC Overview <support/documentation/data_sheets/ds190-Zynq-7000-Overview.pdf>`
 * :xilinx:`Zynq-7000 SoC Packaging and Pinout <support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf>`