analogdevicesinc · PIoandan · Nov 7, 2024 · Nov 1, 2024 · Nov 1, 2024
@@ -0,0 +1,234 @@
+.. _ad7405_fmc:
+
+AD7405-FMC HDL project
+================================================================================
+
+Overview
+-------------------------------------------------------------------------------
+
+The :adi:`EVAL-AD7405` is a full-featured evaluation board
+designed to allow the user to easily evaluate all features of the :adi:`AD7405`
+isolated analog-to-digital converter (ADC).
+
+The provided HDL reference design supports the :adi:`AD7405` , :adi:`AD7403`
+and :adi:`ADuM7701` devices.
+One of the main differences between these devices is the type of the digital
+data lines. In the case of :adi:`ADuM7701` and :adi:`AD7403`, it is
+single-ended, and for :adi:`AD7405` is differential.
+
+Supported boards
+-------------------------------------------------------------------------------
+
+-  :adi:`EVAL-AD7405`
+-  :adi:`EVAL-AD7403`
+-  :adi:`EVAL-ADuM7701`
+
+Supported devices
+-------------------------------------------------------------------------------
+
+-  :adi:`AD7405`
+-  :adi:`AD7403`
+-  :adi:`ADuM7701`
+
+Supported carriers
+-------------------------------------------------------------------------------
+
+.. list-table::
+   :widths: 35 35 30
+   :header-rows: 1
+
+   * - Evaluation board
+     - Carrier
+     - FMC slot
+   * - :adi:`EVAL-AD7405 <EVAL-AD7405>`
+     - :xilinx:`ZedBoard <products/boards-and-kits/1-8dyf-11.html>`
+     - FMC-LPC
+   * - :adi:`EVAL-AD7403 <EVAL-AD7403>`
+     - :xilinx:`ZedBoard <products/boards-and-kits/1-8dyf-11.html>`
+     - FMC-LPC
+   * - :adi:`EVAL-ADuM7701 <EVAL-ADuM7701>`
+     - :xilinx:`ZedBoard <products/boards-and-kits/1-8dyf-11.html>`
+     - FMC-LPC
+
+Block design
+-------------------------------------------------------------------------------
+
+Block diagram
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The data path and clock domains are depicted in the below diagrams:
+
+Block design for the differential signals (:adi:`AD7405`)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. image:: ../ad7405_fmc/ad7405_zed_lvds_diagram.svg
+   :width: 800
+   :align: center
+   :alt: AD7405_FMC/ZedBoard block diagram
+
+Block design for the single-ended signals (:adi:`ADuM7701` and :adi:`AD7403`)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+.. image:: ../ad7405_fmc/ad7405_zed_cmos_diagram.svg
+   :width: 800
+   :align: center
+   :alt: AD7405_FMC/ZedBoard block diagram
+
+Configuration modes
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+-  LVDS_CMOS_N: specific to the type of the data and clock signals
+
+   -  0 - Single-ended data and clock signals (default)
+   -  1 - Differential data and clock signals
+
+CPU/Memory interconnects addresses
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The addresses are dependent on the architecture of the FPGA, having an offset
+added to the base address from HDL (see more at :ref:`architecture`).
+
+==================== ===============
+Instance             Zynq/Microblaze
+==================== ===============
+axi_ad7405_dma       0x44A3_0000
+axi_adc_clkgen       0x44A4_0000
+==================== ===============
+
+GPIOs
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+.. list-table::
+   :widths: 25 20 20 20 15
+   :header-rows: 2
+
+   * - GPIO signal
+     - Direction
+     - HDL GPIO EMIO
+     - Software GPIO
+     - Software GPIO
+   * -
+     - (from FPGA view)
+     -
+     - Zynq-7000
+     - Zynq MP
+   * - filter_reset
+     - INOUT
+     - 48
+     - 102
+     - 124
+   * - decimation_ratio[15:0]
+     - INOUT
+     - 47:32
+     - 101:86
+     - 125:110
+
+Interrupts
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Below are the Programmable Logic interrupts used in this project.
+
+================ === ========== ===========
+Instance name    HDL Linux Zynq Actual Zynq
+================ === ========== ===========
+axi_ad7405_dma   13  57         89
+================ === ========== ===========
+
+Building the HDL project
+-------------------------------------------------------------------------------
+
+The design is built upon ADI's generic HDL reference design framework.
+ADI distributes the bit/elf files of these projects as part of the
+:dokuwiki:`ADI Kuiper Linux <resources/tools-software/linux-software/kuiper-linux>`.
+If you want to build the sources, ADI makes them available on the
+:git-hdl:`HDL repository </>`. To get the source you must
+`clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
+the HDL repository.
+
+Default (Single-ended data and clock signals):
+
+.. code-block::
+   :linenos:
+
+   user@analog:~$ cd hdl/projects/ad7405/zed
+   user@analog:~/hdl/projects/ad7405/zed$ make
+
+If differential data and clock signals are desired:
+
+.. code-block::
+   :linenos:
+
+   user@analog:~$ cd hdl/projects/ad7405/zed
+   user@analog:~/hdl/projects/ad7405/zed$ make LVDS_CMOS_N=1
+
+A more comprehensive build guide can be found in the :ref:`build_hdl` user guide.
+
+Resources
+-------------------------------------------------------------------------------
+
+Systems related
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+-  :dokuwiki:`[Wiki] ADuM7701 - Reference Design <resources/eval/user-guides/adum770x>`
+
+Hardware related
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+-  Product datasheets:
+
+   -  :adi:`AD7405`
+   -  :adi:`AD7403`
+   -  :adi:`ADuM7701`
+
+-  `UG-690, EVAL-AD7405FMCZ User Guide <https://www.analog.com/media/en/technical-documentation/user-guides/EVAL-AD7405FMCZ_UG-690.pdf>`__
+-  `UG-683, EVAL-AD7403FMCZ User Guide <https://www.analog.com/media/en/technical-documentation/user-guides/EVAL-AD7403FMCZ%20_UG-683.pdf>`__
+-  `UG-1525, EV-ADuM7701-8FMCZ User Guide <https://www.analog.com/media/en/technical-documentation/user-guides/EV-ADuM7701-8FMCZ-UG-1525.pdf>`__
+
+HDL related
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+-  :git-hdl:`AD7405-FMC HDL project source code <projects/ad7405_fmc>`
+
+.. list-table::
+   :widths: 30 35 35
+   :header-rows: 1
+
+   * - IP name
+     - Source code link
+     - Documentation link
+   * - AXI_CLKGEN
+     - :git-hdl:`library/axi_clkgen`
+     - :ref:`axi_clkgen`
+   * - AXI_DMAC
+     - :git-hdl:`library/axi_dmac`
+     - :ref:`axi_dmac`
+   * - AXI_HDMI_TX
+     - :git-hdl:`library/axi_hdmi_tx`
+     - :ref:`axi_hdmi_tx`
+   * - AXI_I2S_ADI
+     - :git-hdl:`library/axi_i2s_adi`
+     - ---
+   * - AXI_SPDIF_TX
+     - :git-hdl:`library/axi_spdif_tx`
+     - ---
+   * - AXI_SYSID
+     - :git-hdl:`library/axi_sysid`
+     - :ref:`axi_sysid`
+   * - SYSID_ROM
+     - :git-hdl:`library/sysid_rom`
+     - :ref:`axi_sysid`
+   * - UTIL_DEC256SINC24B
+     - :git-hdl:`library/util_dec256sinc24b`
+     - ---
+   * - UTIL_I2C_MIXER
+     - :git-hdl:`library/util_i2c_mixer`
+     - ---
+
+Software related
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+* No-OS driver at :git-no-os:`legacy/adum7701_fmc`
+
+.. include:: ../common/more_information.rst
+
+.. include:: ../common/support.rst
@@ -35,6 +35,7 @@ Contents
    AD7134-FMC <ad7134_fmc/index>
    AD719X-ASDZ <ad719x_asdz/index>
    AD738X-FMC <ad738x_fmc/index>
+   AD7405-FMC <ad7405_fmc/index>
    AD7606X-FMC <ad7606x_fmc/index>
    AD7616-SDZ <ad7616_sdz/index>
    AD7768-EVB <ad7768evb/index>

@@ -2,8 +2,9 @@
 
 Here are some pointers to help you:
   * [Board Product Page](https://www.analog.com/eval-ad7405)
-  * Parts : [16-Bit, Isolated Sigma-Delta Modulator, LVDS Interface](https://www.analog.com/ad7405)
-  * Parts : [16-Bit, Isolated Sigma-Delta Modulator](https://www.analog.com/adum7701)
-  * Project Doc: 
-  * HDL Doc: 
+  * Parts : [AD7405: 16-Bit, Isolated Sigma-Delta Modulator, LVDS Interface](https://www.analog.com/ad7405)
+  * Parts : [AD7403: 16-Bit, Isolated Sigma-Delta Modulator](https://www.analog.com/ad7403)
+  * Parts : [ADUM7701: 16-Bit, Isolated Sigma-Delta Modulator](https://www.analog.com/adum7701)
+  * Project Doc: https://analogdevicesinc.github.io/hdl/projects/ad7405_fmc/index.html
+  * HDL Doc: https://analogdevicesinc.github.io/hdl/projects/ad7405_fmc/index.html
   * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers-all
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2019-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -24,12 +24,12 @@ ad_ip_parameter axi_ad7405_dma CONFIG.DMA_2D_TRANSFER 0
 ad_ip_parameter axi_ad7405_dma CONFIG.DMA_DATA_WIDTH_SRC 16
 ad_ip_parameter axi_ad7405_dma CONFIG.DMA_DATA_WIDTH_DEST 64
 
-# MCLK generation
+# MCLK generation 50 MHz
 
 ad_ip_instance axi_clkgen axi_adc_clkgen
-ad_ip_parameter axi_adc_clkgen CONFIG.VCO_DIV $clkgen_vco_div
-ad_ip_parameter axi_adc_clkgen CONFIG.VCO_MUL $clkgen_vco_mul
-ad_ip_parameter axi_adc_clkgen CONFIG.CLK0_DIV [expr ($sys_cpu_clk_freq * $clkgen_vco_mul) / ($clkgen_vco_div * $ext_clk_rate)]
+ad_ip_parameter axi_adc_clkgen CONFIG.VCO_DIV 1
+ad_ip_parameter axi_adc_clkgen CONFIG.VCO_MUL 10
+ad_ip_parameter axi_adc_clkgen CONFIG.CLK0_DIV 20
 
 ad_connect adc_clk axi_adc_clkgen/clk_0
 ad_connect sys_cpu_clk axi_adc_clkgen/clk
@@ -49,4 +49,3 @@ ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
 ad_mem_hp2_interconnect sys_cpu_clk axi_ad7405_dma/m_dest_axi
 
 ad_cpu_interrupt "ps-13" "mb-13" axi_ad7405_dma/irq
-
@@ -0,0 +1,5 @@
+FMC_pin   FMC_port         Schematic_name   System_top_name     IOSTANDARD    Termination
+# ad7405 - Single ended signals
+
+G6      FMC_LA00_CC_P       MCLK            adc_clk              LVCMOS25        NA
+G7      FMC_LA00_CC_N       MDAT            adc_data             LVCMOS25        NA
@@ -0,0 +1,7 @@
+FMC_pin   FMC_port         Schematic_name   System_top_name     IOSTANDARD    Termination
+# ad7405 - Differential signals
+
+G6      FMC_LA00_CC_P        MCLKIN+         adc_clk_p          LVDS_25        NA
+G7      FMC_LA00_CC_N        MCLKIN-         adc_clk_n          LVDS_25        NA
+D8      FMC_LA01_CC_P        MDAT+           adc_data_p         LVDS_25        NA
+D9      FMC_LA01_CC_N        MDAT-           adc_data_n         LVDS_25        NA
@@ -6,8 +6,8 @@
 
 PROJECT_NAME := ad7405_fmc_zed
 
-M_DEPS += system_constr_singlended.xdc
-M_DEPS += system_constr_differential.xdc
+M_DEPS += system_constr_cmos.xdc
+M_DEPS += system_constr_lvds.xdc
 M_DEPS += ../common/ad7405_bd.tcl
 M_DEPS += ../../scripts/adi_pd.tcl
 M_DEPS += ../../common/zed/zed_system_constr.xdc

@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2019-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -8,29 +8,16 @@ source $ad_hdl_dir/projects/scripts/adi_pd.tcl
 
 # System clock is 100 MHz for this base design
 
-set sys_cpu_clk_freq  100
-
-# ADC external clock generator configurations, the reference clock is the
-# system clock
-# NOTE: For '7 Series' FPGAs the FVCO must be between 600 MHz and 12000 MHz
-
-set clkgen_vco_div 5
-set clkgen_vco_mul 50
-
-# specify the external clock rate in MHz (MCLKIN)
-
-set ext_clk_rate 25
+source ../common/ad7405_bd.tcl
 
 #system ID
 ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
 ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt"
 ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
 
-set sys_cstring "SYS_CPU_CLK_FREQ=$sys_cpu_clk_freq\
-CLKGEN_VCO_DIV=$clkgen_vco_div\
-CLKGEN_VCO_MUL=$clkgen_vco_mul\
-EXT_CLK_RATE=$ext_clk_rate"
+set sys_cstring "LVDS_CMOS_N=$ad_project_params(LVDS_CMOS_N)"
 
 sysid_gen_sys_init_file $sys_cstring
 
-source ../common/ad7405_bd.tcl
+#To improve timing
+set_property strategy Flow_RunPostRoutePhysOpt [get_runs impl_1]
@@ -1,8 +1,7 @@
 ###############################################################################
-## Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2018-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-set_property -dict {PACKAGE_PIN M19  IOSTANDARD LVCMOS25} [get_ports adc_clk]            ; ## FMC_LPC_LA00_CC_P
-set_property -dict {PACKAGE_PIN M20  IOSTANDARD LVCMOS25} [get_ports adc_data]           ; ## FMC_LPC_LA00_CC_N
-
+set_property -dict {PACKAGE_PIN M19  IOSTANDARD LVCMOS25} [get_ports adc_clk]  ; ## G6  FMC_LA00_CC_P
+set_property -dict {PACKAGE_PIN M20  IOSTANDARD LVCMOS25} [get_ports adc_data] ; ## G7  FMC_LA00_CC_N
@@ -1,10 +1,9 @@
 ###############################################################################
-## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2019-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-set_property -dict {PACKAGE_PIN M19  IOSTANDARD LVDS_25} [get_ports adc_clk_p]          ; ## FMC_LPC_LA00_CC_P
-set_property -dict {PACKAGE_PIN M20  IOSTANDARD LVDS_25} [get_ports adc_clk_n]          ; ## FMC_LPC_LA00_CC_N
-set_property -dict {PACKAGE_PIN N19  IOSTANDARD LVDS_25} [get_ports adc_data_p]         ; ## FMC_LPC_LA01_CC_P
-set_property -dict {PACKAGE_PIN N20  IOSTANDARD LVDS_25} [get_ports adc_data_n]         ; ## FMC_LPC_LA01_CC_N
-
+set_property -dict {PACKAGE_PIN M19  IOSTANDARD LVDS_25} [get_ports adc_clk_p]  ; ## G6  FMC_LA00_CC_P
+set_property -dict {PACKAGE_PIN M20  IOSTANDARD LVDS_25} [get_ports adc_clk_n]  ; ## G7  FMC_LA00_CC_N
+set_property -dict {PACKAGE_PIN N19  IOSTANDARD LVDS_25} [get_ports adc_data_p] ; ## D8  FMC_LA01_CC_P
+set_property -dict {PACKAGE_PIN N20  IOSTANDARD LVDS_25} [get_ports adc_data_n] ; ## D9  FMC_LA01_CC_N