Add AD4052-ARDZ project #1504
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Add AD4052-ARDZ project #1504
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gastmaier
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IuliaCMoldovan,
StancaPop,
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acostina,
AndreiGrozav,
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sarpadi
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6 tasks
sarpadi
reviewed
Nov 11, 2024
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Applied review changes. |
sarpadi
reviewed
Dec 3, 2024
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| assign adc_cnv = adc_cnv_w | (gpio_o[34] & ~gpio_t[34]); | ||
| assign gpio_i[34] = adc_cnv; |
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why is this level of CNV control not available on the de10nano approach ?
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Merge after #1517 |
sarpadi
previously approved these changes
Dec 18, 2024
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Describe EVAL-AD4052-ARDZ support with coraz7s. Signed-off-by: Jorge Marques <jorge.marques@analog.com>
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Forced pushed to increase Coraz7S spi_clk from 150 to 180Hz -> fscl 45MHz (180/((1+1)*2)) |
sarpadi
approved these changes
Dec 19, 2024
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PR Description
Adds support to the AD4052 ADC SPI family (AD4050, AD4052, AD4056, AD4058).
The CNV pin contains a OR logic for:
SPI Engine Offload waits the Data Ready signal from the ADC, configured at pin GP1.
ADC GP0 is used as a monitor pin, triggering either threshold (rising+failing) events to the PS.
Named ad4052 instead of ad405x since the ad4052 is the main part of the family (best granularity and speed).
Pointers:
www.analog.com/ad4050
www.analog.com/ad4052
www.analog.com/eval-ad4052-ardz.html
Coraz7s tested on HW. Pending De10Nano
The de10nano raises the same critical warnings as #1463
PR Type
PR Checklist