Ad4630x refactor #1964
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Ad4630x refactor #1964
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caosjr
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Looks good, builds fine, makes parametrization nicer, and fixes the weird usage for 1ch.
A few minor comments only.
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Separates the 1CH (AD4030) HDL support from the 2CH (AD4630) support. Previously, whenever 1CH was used it was necessary to throw away half of the data because the project was always expecting 2 channels for the ADC. Updated the XDC files for each supported mode considering how the amount of channels the ADC. Also updated the tcl script variables, now there is a NUM_OF_CHANNEL, updated the NUM_OF_SDI to LANES_PER_CHANNEL, and inserted INTERLEAVE_MODE variable. NO_REORDER became an internal compilation variable that is enabled according to the combination NUM_OF_CHANNEL, LANES_PER_CHANNEL and INTERLEAVE_MODE. Setting INTERLEAVE_MODE to 1 with unsupported configuration throws an error. Inserts a GPIO to drive CNV pin in parallel with the PWM. The CNV pin is an "or" function of the GPIO[36] and PWM. Updated examples in the README FILE. Signed-off-by: Carlos Souza <carlos.souza@analog.com>
Updated the documentation with the new variables and features of the AD4630_FMC project. It is describing how to compile with the NUM_OF_CHANNEL, LANES_PER_CHANNEL, and INTERLEAVE_MODE. It also describes the EMIO inserted for controlling the CNV output. Signed-off-by: Carlos Souza <carlos.souza@analog.com>
Signed-off-by: Carlos Souza <carlos.souza@analog.com>
The constraint file requires ad463x_spi_sdi[0] instead of ad463x_spi_sdi. This commit fixes all the variations with a single channel a single lane. Signed-off-by: Carlos Souza <carlos.souza@analog.com>
updated README examples with the supported modes. Signed-off-by: Carlos Souza <carlos.souza@analog.com>
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| # data is latched on negative edge | ||
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| set tsetup 5.6 | ||
| set thold 1.6 |
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Why does this one and the 8 sdi one have a different hold time?
| switch [get_env_param LANES_PER_CHANNEL 2] { | ||
| 1 { | ||
| # For 1 SDI, check NUM_OF_CHANNEL | ||
| # For 1 lane per channel, check NUM_OF_CHANNEL |
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I looked back at the doc, and we were using line instead of lane there. I know I was talking about lanes before, but keeping consistent with line is much better for this, andlane might be associated with high-speed differential signals.
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| # For 1 lane per channel, check NUM_OF_CHANNEL | |
| # For 1 line per channel, check NUM_OF_CHANNEL |
also for other instances of "lane"
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This PR updates the TCL scripts for generating the correct controller for 1-channel or 2-channel ADC. In that manner, the programmer does not have to select the useful data when it is using a single channel ADC.
For that, it was added NUM_OF_CHANNEL and LANES_PER_CHANNEL variables. Interleave mode is now available under the INTERLEAVE_MODE variable, which only works with NUM_OF_CHANNEL=2 and LANES_PER_CHANNEL=1. NO_REORDER is an internal variable now that is enabled according to the configuration set.
Added GPIO support for CNV so the software can control the CNV in parallel with the PWM core.
Updated the testbench for those new features: https://github.com/analogdevicesinc/testbenches/tree/ad4630_update
Updated the documentation for describing the new features.
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