Dev ad974x fmc wip #1974
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Dev ad974x fmc wip #1974
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Signed-off-by: Liviu 'Ceshu' Adace <liviu.adace@analog.com> Signed-off-by: sarpadi <sergiu.arpadi@analog.com>
Signed-off-by: Liviu 'Ceshu' Adace <liviu.adace@analog.com> Signed-off-by: sarpadi <sergiu.arpadi@analog.com>
Signed-off-by: Liviu 'Ceshu' Adace <liviu.adace@analog.com> Signed-off-by: sarpadi <sergiu.arpadi@analog.com>
Signed-off-by: Liviu 'Ceshu' Adace <liviu.adace@analog.com> Signed-off-by: sarpadi <sergiu.arpadi@analog.com>
Signed-off-by: sarpadi <sergiu.arpadi@analog.com>
sarpadi
requested review from
AndreiGrozav,
IuliaCMoldovan,
LBFFilho,
PopPaul2021,
StancaPop,
acostina and
gastmaier
as code owners
Collaborator
|
RetriggerCI |
LBFFilho
reviewed
Jan 12, 2026
Signed-off-by: sarpadi <sergiu.arpadi@analog.com>
Signed-off-by: sarpadi <sergiu.arpadi@analog.com>
Signed-off-by: sarpadi <sergiu.arpadi@analog.com>
Signed-off-by: sarpadi <sergiu.arpadi@analog.com>
Collaborator
|
RetriggerCI |
LBFFilho
requested changes
Jan 20, 2026
Comment on lines
45
to
52
| # Multicycle path constraint | ||
| # Due to the clock architecture where AD9744 receives clock directly from ADF4351 while | ||
| # FPGA sees the same clock after IBUFDS+BUFG delays (~5.1ns), the data path takes longer | ||
| # than one clock period. Data arrives at ~8.6ns but needs to be sampled at edge 2 (~9.5ns). | ||
| # Allow 3 cycles for setup to ensure positive slack | ||
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| set_multicycle_path -setup -to [get_ports ad9740_data[*]] 3 | ||
| set_multicycle_path -hold -to [get_ports ad9740_data[*]] 2 |
Contributor
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I think we want this without the set_multicycle_path -hold constraint. This constraint relaxes the hold checks to be relative to the same as the launch edge, making this path a "only one every N" case. My understanding is that we want to send valid data every cycle, so we need the hold path to also be relative to the delayed edge.
Signed-off-by: sarpadi <sergiu.arpadi@analog.com>
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PR Description
Adding the AXI_AD9740 core and AD9740 Zed based HDL project together with documentation
PR Type
PR Checklist