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arm: dts: Update coraz7s to match changes on the hdl. #2657

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Dec 6, 2024
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66 changes: 0 additions & 66 deletions arch/arm/boot/dts/xilinx/zynq-coraz7s-cn0501.dts

This file was deleted.

28 changes: 10 additions & 18 deletions arch/arm/boot/dts/xilinx/zynq-coraz7s-cn0540.dts
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,7 @@
*/
/dts-v1/;
#include "zynq-coraz7s.dtsi"
#include "zynq-coraz7s-iic.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>

Expand Down Expand Up @@ -121,7 +122,7 @@
compatible = "adi,axi-spi-engine-1.00.a";
reg = <0x44a00000 0x10000>;
interrupt-parent = <&intc>;
interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc 15 &spi_clk>;
clock-names = "s_axi_aclk", "spi_clk";
num-cs = <1>;
Expand All @@ -148,23 +149,6 @@
};
};

axi_i2c_0:axi-iic@0x44a40000{
compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a";
reg = <0x44a40000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc 15>;

#address-cells = <1>;
#size-cells = <0>;

ltc2606: ltc2606@10 {
compatible = "adi,ltc2606";
reg = <0x10>;
vref-supply = <&vref>;
};
};

spi_clk: axi-clkgen@0x44a70000 {
compatible = "adi,axi-clkgen-2.00.a";
reg = <0x44a70000 0x10000>;
Expand All @@ -174,3 +158,11 @@
clock-output-names = "spi_clk";
};
};

&axi_i2c_0 {
ltc2606: ltc2606@10 {
compatible = "adi,ltc2606";
reg = <0x10>;
vref-supply = <&vref>;
};
};
29 changes: 10 additions & 19 deletions arch/arm/boot/dts/xilinx/zynq-coraz7s-cn0579_i2c.dts
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@
*/
/dts-v1/;
#include "zynq-coraz7s.dtsi"
#include "zynq-coraz7s-iic.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>

Expand Down Expand Up @@ -66,26 +67,8 @@
reg = <0x44a30000 0x1000>;
#dma-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc 16>;
};

axi_i2c_0: i2c@44a40000{
compatible = "xlnx,axi-iic-1.02.a", "xlnx,xps-iic-2.00.a";
reg = <0x44a40000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc 15>;

#address-cells = <1>;
#size-cells = <0>;

ad5696: dac@c {
compatible = "adi,ad5696";
reg = <0x0c>;
vref-supply = <&vref>;

};
clocks = <&clkc 16>;
};

axi_adc_ad7768: cf_axi_adc@44a00000{
Expand All @@ -97,6 +80,14 @@
};
};

&axi_i2c_0 {
ad5696: dac@c {
compatible = "adi,ad5696";
reg = <0x0c>;
vref-supply = <&vref>;
};
};

&spi0 {
status = "okay";

Expand Down
8 changes: 8 additions & 0 deletions arch/arm/boot/dts/xilinx/zynq-coraz7s.dts
Original file line number Diff line number Diff line change
Expand Up @@ -3,3 +3,11 @@

/dts-v1/;
#include "zynq-coraz7s.dtsi"
#include "zynq-coraz7s-iic.dtsi"

&axi_i2c_0 {
eeprom1: eeprom@50 {
compatible = "at24,24c02";
reg = <0x50>;
};
};
16 changes: 16 additions & 0 deletions arch/arm/boot/dts/zynq-coraz7s-iic.dtsi
Original file line number Diff line number Diff line change
@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (C) 2024 Analog Devices Inc. */

&fpga_axi {
axi_i2c_0: i2c@41600000 {
compatible = "xlnx,axi-iic-1.01.b", "xlnx,xps-iic-2.00.a";
reg = <0x41600000 0x10000>;
interrupt-parent = <&intc>;
interrupts = <0 55 4>;
clocks = <&clkc 15>;
clock-names = "pclk";

#size-cells = <0>;
#address-cells = <1>;
};
};
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