i3c_controller: Add testbench project

Signed-off-by: Jorge Marques <jorge.marques@analog.com>

ad405x_i3c_ardz/Makefile

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+####################################################################################
+####################################################################################
+## Copyright (C) 2024 Analog Devices, Inc.
+####################################################################################
+####################################################################################
+
+# All test-bench dependencies except test programs
+SV_DEPS += ../common/sv/utils.svh
+SV_DEPS += ../common/sv/logger_pkg.sv
+SV_DEPS += ../common/sv/reg_accessor.sv
+SV_DEPS += ../common/sv/m_axis_sequencer.sv
+SV_DEPS += ../common/sv/s_axis_sequencer.sv
+SV_DEPS += ../common/sv/m_axi_sequencer.sv
+SV_DEPS += ../common/sv/s_axi_sequencer.sv
+SV_DEPS += ../common/sv/dmac_api.sv
+SV_DEPS += ../common/sv/adi_regmap_pkg.sv
+SV_DEPS += ../common/sv/adi_regmap_dmac_pkg.sv
+SV_DEPS += ../common/sv/dma_trans.sv
+SV_DEPS += ../common/sv/axi_dmac_pkg.sv
+SV_DEPS += system_tb.sv
+
+ENV_DEPS +=../../library/util_cdc/sync_bits.v
+ENV_DEPS +=../../library/common/ad_edge_detect.v
+
+ENV_DEPS += system_project.tcl
+ENV_DEPS += system_bd.tcl
+ENV_DEPS +=../scripts/adi_sim.tcl
+ENV_DEPS +=../scripts/run_sim.tcl
+
+LIB_DEPS += axi_dmac
+LIB_DEPS += axi_sysid
+LIB_DEPS += i3c_controller/i3c_controller_host_interface
+LIB_DEPS += i3c_controller/i3c_controller_core
+LIB_DEPS += sysid_rom
+
+# default test program
+TP := test_program
+
+# config files should have the following format
+#  cfg_<param1>_<param2>.tcl
+CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl))
+#$(warning $(CFG_FILES))
+
+# List of tests and configuration combinations that has to be run
+# Format is:  <configuration>:<test name>
+TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(cfg):$(TP))
+
+include ../scripts/project-sim.mk
+
+# usage :
+#
+# run specific test on a specific configuration in gui mode
+# 	make CFG=cfg1 TST=test_program MODE=gui
+#
+# run all test from a configuration
+# 	make cfg1
+
+####################################################################################
+####################################################################################

ad405x_i3c_ardz/README.md

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+Usage :
+
+Run all tests in batch mode:
+
+	make
+
+
+Run all tests in GUI mode:
+
+	make MODE=gui
+
+
+Run specific test on a specific configuration in gui mode:
+
+	make CFG=<name of cfg> TST=<name of test> MODE=gui
+
+
+Run all test from a configuration:
+
+	make <name of cfg>
+
+
+Where:
+
+ * <name of cfg> is a file from the cfgs directory without the tcl extension of format cfg\*
+ * <name of test> is a file from the tests directory without the tcl extension
+

ad405x_i3c_ardz/cfgs/cfg1.tcl

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+global ad_project_params

ad405x_i3c_ardz/system_bd.tcl

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+# ***************************************************************************
+# ***************************************************************************
+# Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+#
+# In this HDL repository, there are many different and unique modules, consisting
+# of various HDL (Verilog or VHDL) components. The individual modules are
+# developed independently, and may be accompanied by separate and unique license
+# terms.
+#
+# The user should read each of these license terms, and understand the
+# freedoms and responsibilities that he or she has by using this source/core.
+#
+# This core is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+# A PARTICULAR PURPOSE.
+#
+# Redistribution and use of source or resulting binaries, with or without modification
+# of this file, are permitted under one of the following two license terms:
+#
+#   1. The GNU General Public License version 2 as published by the
+#      Free Software Foundation, which can be found in the top level directory
+#      of this repository (LICENSE_GPL2), and also online at:
+#      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+#
+# OR
+#
+#   2. An ADI specific BSD license, which can be found in the top level directory
+#      of this repository (LICENSE_ADIBSD), and also on-line at:
+#      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+#      This will allow to generate bit files and not release the source code,
+#      as long as it attaches to an ADI device.
+#
+# ***************************************************************************
+# ***************************************************************************
+
+source ../../scripts/adi_env.tcl
+
+global ad_project_params
+
+adi_project_files [list \
+	"../../library/common/ad_edge_detect.v" \
+	"../../library/util_cdc/sync_bits.v" \
+        "../../library/common/ad_iobuf.v" \
+]
+
+#
+#  Block design under test
+#
+
+source ../../projects/ad405x_i3c_ardz/common/ad405x_i3c_ardz_bd.tcl
+
+create_bd_port -dir O i3c_irq
+create_bd_port -dir O i3c_clk
+
+ad_connect i3c_irq i3c_controller_0/irq
+ad_connect i3c_clk sys_clk_vip/clk_out

ad405x_i3c_ardz/system_project.tcl

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+# ***************************************************************************
+# ***************************************************************************
+# Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+#
+# In this HDL repository, there are many different and unique modules, consisting
+# of various HDL (Verilog or VHDL) components. The individual modules are
+# developed independently, and may be accompanied by separate and unique license
+# terms.
+#
+# The user should read each of these license terms, and understand the
+# freedoms and responsibilities that he or she has by using this source/core.
+#
+# This core is distributed in the hope that it will be useful, but WITHOUT ANY
+# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+# A PARTICULAR PURPOSE.
+#
+# Redistribution and use of source or resulting binaries, with or without modification
+# of this file, are permitted under one of the following two license terms:
+#
+#   1. The GNU General Public License version 2 as published by the
+#      Free Software Foundation, which can be found in the top level directory
+#      of this repository (LICENSE_GPL2), and also online at:
+#      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+#
+# OR
+#
+#   2. An ADI specific BSD license, which can be found in the top level directory
+#      of this repository (LICENSE_ADIBSD), and also on-line at:
+#      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+#      This will allow to generate bit files and not release the source code,
+#      as long as it attaches to an ADI device.
+#
+# ***************************************************************************
+# ***************************************************************************
+
+source ../scripts/adi_sim.tcl
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+if {$argc < 1} {
+  puts "Expecting at least one argument that specifies the test configuration"
+  exit 1
+} else {
+  set cfg_file [lindex $argv 0]
+}
+
+# Read common config file
+source "cfgs/${cfg_file}"
+
+# Set the project name
+set project_name [file rootname $cfg_file]
+
+# Create the project
+adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e"
+
+# Add test files to the project
+adi_sim_project_files [list \
+ "../common/sv/utils.svh" \
+ "../common/sv/logger_pkg.sv" \
+ "../common/sv/reg_accessor.sv" \
+ "../common/sv/m_axis_sequencer.sv" \
+ "../common/sv/s_axis_sequencer.sv" \
+ "../common/sv/m_axi_sequencer.sv" \
+ "../common/sv/s_axi_sequencer.sv" \
+ "../common/sv/dmac_api.sv" \
+ "../common/sv/adi_regmap_pkg.sv" \
+ "../common/sv/adi_regmap_dmac_pkg.sv" \
+ "../common/sv/dma_trans.sv" \
+ "../common/sv/axi_dmac_pkg.sv" \
+ "../common/sv/test_harness_env.sv" \
+ "tests/test_program.sv" \
+ "system_tb.sv" \
+ ]
+
+#set a default test program
+adi_sim_add_define "TEST_PROGRAM=test_program"
+
+adi_sim_generate $project_name

ad405x_i3c_ardz/system_tb.sv

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+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsabilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/1ps
+
+`include "utils.svh"
+
+module system_tb();
+  wire i3c_irq;
+  wire i3c_clk;
+  wire i3c_scl;
+  wire i3c_sda;
+  wire i3c_sdi;
+  wire i3c_sdo;
+  wire i3c_t;
+
+  ad_iobuf #(
+    .DATA_WIDTH(1)
+  ) i_iobuf_sda (
+    .dio_t(i3c_t),
+    .dio_i(i3c_sdo),
+    .dio_o(i3c_sdi),
+    .dio_p(i3c_sda));
+
+  `TEST_PROGRAM test(
+    .i3c_irq(i3c_irq),
+    .i3c_clk(i3c_clk),
+    .i3c_controller_0_scl(i3c_scl),
+    .i3c_controller_0_sda(i3c_sda));
+
+  test_harness `TH (
+    .i3c_irq(i3c_irq),
+    .i3c_clk(i3c_clk),
+    .i3c_controller_0_scl(i3c_scl),
+    .i3c_controller_0_sdi(i3c_sdi),
+    .i3c_controller_0_sdo(i3c_sdo),
+    .i3c_controller_0_t(i3c_t));
+
+endmodule