Added a new testbench for checking the SPI Engine Sleep and Chip Select Instruction delays #49
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Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
…eep duration Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Both of these tests test related features, which are implemented in a related way on the DUT. The tests were kept separate from the default ones since they are specific to this functionality. Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Changed comments on test_sleep_delay.sv for accuracy. Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
gastmaier
requested changes
Oct 18, 2023
- Removed unnecessary whitespace - Created a .svh header file with SPI Engine registers, now used by both tests - Used sleep macro to the sleep test task parametrization more legible - Removed excessive nesting on pass/fail conditions - Removed unneeded comments Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
gastmaier
approved these changes
Oct 20, 2023
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Squash and merge when analogdevicesinc/hdl#1200 gets approved too |
…s for command FIFO Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
gastmaier
requested changes
Oct 23, 2023
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
gastmaier
approved these changes
Oct 24, 2023
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
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This PR creates a separate test, which was used on creating this other PR to the hdl repo. The aim of these PRs is to address some incosistencies with the sleep and delay behaviors on the Sleep and Chip Select instructions. To run the tests, simply cd to the testbenches/pulsar_adc_pmdz directory, and run:
make TST=sleep_delay_testFor more information about the specifig bug fixes, please look at the PR on the hdl repository:
SPI Engine: Fixed delay behaviour on Chip-Select and Sleep instructions