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[#67375] Follow rename of cosimulation components
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adrabarek committed Oct 21, 2024
1 parent 809d161 commit cf60bb8
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Showing 11 changed files with 36 additions and 36 deletions.
52 changes: 26 additions & 26 deletions cmake/build-cosimulation.cmake
Original file line number Diff line number Diff line change
Expand Up @@ -11,9 +11,9 @@ endif()

if(NOT USER_RENODE_DIR AND DEFINED ENV{RENODE_ROOT})
message(STATUS "Using RENODE_ROOT from environment as USER_RENODE_DIR")
set(USER_RENODE_DIR $ENV{RENODE_ROOT} CACHE PATH "Absolute (!) path to Renode root directory or any other that contains VerilatorIntegrationLibrary.")
set(USER_RENODE_DIR $ENV{RENODE_ROOT} CACHE PATH "Absolute (!) path to Renode root directory or any other that contains CoSimulationLibrary.")
else()
set(USER_RENODE_DIR CACHE PATH "Path to Renode root directory or any other that contains VerilatorIntegrationLibrary, relative to build directory.")
set(USER_RENODE_DIR CACHE PATH "Path to Renode root directory or any other that contains CoSimulationLibrary, relative to build directory.")
get_filename_component(USER_RENODE_DIR "${USER_RENODE_DIR}" ABSOLUTE BASE_DIR ${CMAKE_CURRENT_BINARY_DIR})
endif()

Expand Down Expand Up @@ -68,36 +68,36 @@ if(CMAKE_HOST_WIN32)
endif()
endif()

if(NOT VIL_DIR)
if(NOT COLIB_DIR)
if(NOT USER_RENODE_DIR OR NOT IS_ABSOLUTE "${USER_RENODE_DIR}")
message(FATAL_ERROR "Please set the CMake's USER_RENODE_DIR variable to an absolute (!) path to Renode root directory or any other that contains VerilatorIntegrationLibrary.\nPass the '-DUSER_RENODE_DIR=<ABSOLUTE_PATH>' switch if you configure with the 'cmake' command. Optionally, consider using 'ccmake' or 'cmake-gui' which make it easier.")
message(FATAL_ERROR "Please set the CMake's USER_RENODE_DIR variable to an absolute (!) path to Renode root directory or any other that contains CoSimulationLibrary.\nPass the '-DUSER_RENODE_DIR=<ABSOLUTE_PATH>' switch if you configure with the 'cmake' command. Optionally, consider using 'ccmake' or 'cmake-gui' which make it easier.")
endif()
message(STATUS "Looking for Renode VerilatorIntegrationLibrary inside ${USER_RENODE_DIR}...")
set(VIL_FILE verilator-integration-library.cmake)
file(GLOB_RECURSE VIL_FOUND ${USER_RENODE_DIR}/*/${VIL_FILE})

list(LENGTH VIL_FOUND VIL_FOUND_N)
if(${VIL_FOUND_N} EQUAL 1)
string(REPLACE "/${VIL_FILE}" "" VIL_DIR ${VIL_FOUND})
elseif(${VIL_FOUND_N} GREATER 1)
string(REGEX REPLACE "/${VIL_FILE}" " " ALL_FOUND ${VIL_FOUND})
message(FATAL_ERROR "Found more than one directory with VerilatorIntegrationLibrary inside USER_RENODE_DIR. Please choose one of them: ${ALL_FOUND}")

message(STATUS "Looking for Renode CoSimulationLibrary inside ${USER_RENODE_DIR}...")
set(COLIB_FILE cosimulation-library.cmake)
file(GLOB_RECURSE COLIB_FOUND ${USER_RENODE_DIR}/*/${COLIB_FILE})

list(LENGTH COLIB_FOUND COLIB_FOUND_N)
if(${COLIB_FOUND_N} EQUAL 1)
string(REPLACE "/${COLIB_FILE}" "" COLIB_DIR ${COLIB_FOUND})
elseif(${COLIB_FOUND_N} GREATER 1)
string(REGEX REPLACE "/${COLIB_FILE}" " " ALL_FOUND ${COLIB_FOUND})
message(FATAL_ERROR "Found more than one directory with CoSimulationLibrary inside USER_RENODE_DIR. Please choose one of them: ${ALL_FOUND}")
endif()

if(NOT VIL_DIR OR NOT EXISTS "${VIL_DIR}/${VIL_FILE}")
message(FATAL_ERROR "Couldn't find valid VerilatorIntegrationLibrary inside USER_RENODE_DIR!")
if(NOT COLIB_DIR OR NOT EXISTS "${COLIB_DIR}/${COLIB_FILE}")
message(FATAL_ERROR "Couldn't find valid CoSimulationLibrary inside USER_RENODE_DIR!")
endif()

include(${VIL_DIR}/${VIL_FILE}) # sets VIL_VERSION variable
message(STATUS "Renode VerilatorIntegrationLibrary (version ${VIL_VERSION}) found in ${VIL_DIR}.")
include(${COLIB_DIR}/${COLIB_FILE}) # sets COLIB_VERSION variable
message(STATUS "Renode CoSimulationLibrary (version ${COLIB_VERSION}) found in ${COLIB_DIR}.")

# Save VIL_DIR in cache
set(VIL_DIR ${VIL_DIR} CACHE INTERNAL "")
# Save COLIB_DIR in cache
set(COLIB_DIR ${COLIB_DIR} CACHE INTERNAL "")
endif()

# Prepare list of Renode DPI Integration files
set(RENODE_HDL_LIBRARY ${VIL_DIR}/hdl)
set(RENODE_HDL_LIBRARY ${COLIB_DIR}/hdl)
set(RENODE_HDL_INCLUDE_DIRS ${RENODE_HDL_LIBRARY})

file(GLOB RENODE_HDL_SOURCES ${RENODE_HDL_LIBRARY}/imports/*.sv)
Expand All @@ -110,9 +110,9 @@ foreach(PATH ${RENODE_HDL_MODULES})
endif()
endforeach()

file(GLOB_RECURSE RENODE_SOURCES ${VIL_DIR}/libs/socket-cpp/*.cpp)
list(APPEND RENODE_SOURCES ${VIL_DIR}/src/communication/socket_channel.cpp)
list(APPEND RENODE_SOURCES ${VIL_DIR}/src/renode_dpi.cpp)
file(GLOB_RECURSE RENODE_SOURCES ${COLIB_DIR}/libs/socket-cpp/*.cpp)
list(APPEND RENODE_SOURCES ${COLIB_DIR}/src/communication/socket_channel.cpp)
list(APPEND RENODE_SOURCES ${COLIB_DIR}/src/renode_dpi.cpp)

if(NOT SIM_TOP OR NOT SIM_TOP_FILE)
message(FATAL_ERROR "'SIM_TOP' and 'SIM_TOP_FILE' variable have to be set!")
Expand Down Expand Up @@ -167,7 +167,7 @@ else()
message(FATAL_ERROR "'VERILATOR_CSOURCES' it's required to set this variable for Verilator target!")
endif()
add_executable(verilated ${VERILATOR_CSOURCES} ${RENODE_SOURCES})
target_include_directories(verilated PRIVATE ${VIL_DIR})
target_include_directories(verilated PRIVATE ${COLIB_DIR})
target_compile_options(verilated PRIVATE ${FINAL_COMP_ARGS})
target_link_libraries(verilated PRIVATE ${FINAL_LINK_ARGS})
verilate(verilated SOURCES ${FINAL_SIM_FILES} TOP_MODULE ${SIM_TOP} PREFIX "V${SIM_TOP}" VERILATOR_ARGS ${FINAL_VERILATOR_ARGS})
Expand Down
2 changes: 1 addition & 1 deletion samples/ahb_dma/platform.repl
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
dma: Verilated.VerilatedPeripheral @ sysbus <0x10000000, +0x100>
dma: CoSimulated.CoSimulatedPeripheral @ sysbus <0x10000000, +0x100>
maxWidth: 32
limitBuffer: 1000000
timeout: 10000
Expand Down
2 changes: 1 addition & 1 deletion samples/ahb_mem/platform.repl
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
mem: Verilated.VerilatedPeripheral @ sysbus <0x20000000, +0x100000>
mem: CoSimulated.CoSimulatedPeripheral @ sysbus <0x20000000, +0x100000>
// NOTE: Bus is 32-bit; this is set to 64 bit to test the behavior
// of invalid 64-bit access on HDL level
maxWidth: 64
Expand Down
2 changes: 1 addition & 1 deletion samples/ahb_simple_manager/platform.repl
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
ahb_subordinate: Verilated.VerilatedPeripheral @ sysbus <0x10000000, +0x100>
ahb_subordinate: CoSimulated.CoSimulatedPeripheral @ sysbus <0x10000000, +0x100>
maxWidth: 32
limitBuffer: 1000000
timeout: 5000
Expand Down
2 changes: 1 addition & 1 deletion samples/apb3_completer_mem/platform.repl
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
mem: Verilated.VerilatedPeripheral @ sysbus <0x0, +0x10000>
mem: CoSimulated.CoSimulatedPeripheral @ sysbus <0x0, +0x10000>
// Note: QuadWord accesses will be truncated to the APB3 bus width (32-bits in this example)
maxWidth: 64
limitBuffer: 1000000
Expand Down
2 changes: 1 addition & 1 deletion samples/apb3_requester_synth/platform.repl
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
requester: Verilated.VerilatedPeripheral @ sysbus <0x10000000, +0x100>
requester: CoSimulated.CoSimulatedPeripheral @ sysbus <0x10000000, +0x100>
maxWidth: 32
limitBuffer: 1000000
timeout: 5000
Expand Down
2 changes: 1 addition & 1 deletion samples/axi_fastvdma/platform_basic.repl
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
dma: Verilated.VerilatedPeripheral @ sysbus <0x10000000, +0x100>
dma: CoSimulated.CoSimulatedPeripheral @ sysbus <0x10000000, +0x100>
maxWidth: 32
limitBuffer: 1000000
timeout: 5000
Expand Down
2 changes: 1 addition & 1 deletion samples/axi_fastvdma/platform_linux.repl
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
using "platforms/boards/zedboard.repl"

dma: Verilated.VerilatedPeripheral @ sysbus <0x43c20000, +0x100>
dma: CoSimulated.CoSimulatedPeripheral @ sysbus <0x43c20000, +0x100>
maxWidth: 32
// Changing frequency to a non-default value breaks timings in a trace.
// But it improves a performance of Linux simulation.
Expand Down
2 changes: 1 addition & 1 deletion samples/axi_fastvdma_prebuilt/platform.repl
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
using "platforms/boards/zedboard.repl"

dma: Verilated.VerilatedPeripheral @ sysbus <0x43c20000, +0x100>
dma: CoSimulated.CoSimulatedPeripheral @ sysbus <0x43c20000, +0x100>
maxWidth: 32
// Changing frequency to a non-default value breaks timings in a trace.
// But it improves a performance of Linux simulation.
Expand Down
2 changes: 1 addition & 1 deletion samples/axi_ram/platform.repl
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
mem: Verilated.VerilatedPeripheral @ sysbus <0x20000000, +0x100000>
mem: CoSimulated.CoSimulatedPeripheral @ sysbus <0x20000000, +0x100000>
maxWidth: 64
limitBuffer: 1000000
timeout: 10000
Expand Down
2 changes: 1 addition & 1 deletion samples/gpio_repeater/platform.repl
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
repeater: Verilated.VerilatedPeripheral @ sysbus <0x100, +0x4>
repeater: CoSimulated.CoSimulatedPeripheral @ sysbus <0x100, +0x4>
address: "127.0.0.1"
timeout: 100000
maxWidth: 64
Expand Down

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