Add option to build command to specify build directory

This lets the user pick where they want the resulting files generated.
Previously it defaulted to "build" in the current working directory.

Signed-off-by: Krzysztof Obłonczek <koblonczek@internships.antmicro.com>

fpga_topwrap/cli.py

@@ -23,13 +23,20 @@
     "--sources", "-s", type=click_dir, help="Specify directory to scan for additional sources"
 )
 @click.option("--design", "-d", type=click_file, required=True, help="Specify top design file")
+@click.option(
+    "--build-dir",
+    "-b",
+    type=click_dir,
+    default="build",
+    help="Specify directory for output files. Directory must exist",
+)
 @click.option("--part", "-p", help="FPGA part name")
 @click.option(
     "--iface-compliance/--no-iface-compliance",
     default=False,
     help="Force compliance checks for predefined interfaces",
 )
-def build_main(sources, design, part, iface_compliance):
+def build_main(sources, design, build_dir, part, iface_compliance):
     config.force_interface_compliance = iface_compliance
 
     if part is None:
@@ -38,7 +45,7 @@ def build_main(sources, design, part, iface_compliance):
             "and thus your implamentation may fail."
         )
 
-    build_design_from_yaml(design, sources, part)
+    build_design_from_yaml(design, build_dir, sources, part)
 
 
 @main.command("parse", help="Parse HDL sources to ip core yamls")

fpga_topwrap/design.py

@@ -10,10 +10,10 @@
 from .ipwrapper import IPWrapper
 
 
-def build_design_from_yaml(yamlfile, sources_dir=None, part=None):
+def build_design_from_yaml(yamlfile, build_dir, sources_dir=None, part=None):
     with open(yamlfile) as f:
         design = load(f, Loader=Loader)
-    build_design(design, sources_dir, part)
+    build_design(design, build_dir, sources_dir, part)
 
 
 def get_hierarchies_names(design_descr: dict) -> set:
@@ -99,7 +99,7 @@ def generate_design(ips: dict, design: dict, external: dict) -> IPConnect:
     return ipc
 
 
-def build_design(design_descr, sources_dir=None, part=None):
+def build_design(design_descr, build_dir, sources_dir=None, part=None):
     """Build a complete project
 
     :param design: dict describing the top design
@@ -113,4 +113,4 @@ def build_design(design_descr, sources_dir=None, part=None):
     design_name = design["name"] if "name" in design else "top"
 
     ipc = generate_design(design_descr["ips"], design, external)
-    ipc.build(sources_dir=sources_dir, part=part, top_module_name=design_name)
+    ipc.build(build_dir=build_dir, sources_dir=sources_dir, part=part, top_module_name=design_name)

tests/tests_build/test_design.py

@@ -6,4 +6,4 @@ class TestDesign:
     def test_design(self):
         from fpga_topwrap.design import build_design_from_yaml
 
-        build_design_from_yaml("tests/data/data_build/design.yaml")
+        build_design_from_yaml("tests/data/data_build/design.yaml", "build")