Reformat all non-python files

docs/source/cli.md

@@ -26,7 +26,7 @@ python -m fpga_topwrap build --sources src --design project.yml --part 'xc7z020c
 
 ## Connect Topwrap to Pipeline Manager
 
-If you want to use Pipeline Manager as a UI for creating block design, you need to: 
+If you want to use Pipeline Manager as a UI for creating block design, you need to:
 
 1. Build and run Pipeline Manager server application.
 

docs/source/description_files.md

@@ -210,4 +210,3 @@ signals:
 ```
 
 The name of an interface has to be unique. We also specify a prefix which will be used as a shortened identifier.
-

docs/source/ipwrapper.md

@@ -9,4 +9,3 @@ It's used to standardize names of ports that belong to interfaces to ease connec
 
    .. automethod:: __init__
 ```
-

docs/source/wrapper_port.md

@@ -22,4 +22,3 @@ This is used in {code}`IPWrapper` class implementation and there should be no ne
 
    .. automethod:: __init__
 ```
-

examples/hdmi/project.yml

@@ -143,7 +143,7 @@ ports:
     HDMI_D1_P: HDMI_D1_P
     HDMI_D1_N: HDMI_D1_N
     HDMI_D2_P: HDMI_D2_P
-    HDMI_D2_N: HDMI_D2_N 
+    HDMI_D2_N: HDMI_D2_N
 
 interfaces:
   ps7:

examples/hdmi/sources/ps7.v

@@ -116,7 +116,7 @@ module ps7_inst (
 );
     wire [ 3: 0] FCLK;
     wire  [19: 0] IRQF2P;
-    
+
     assign FCLK0 = FCLK[0];
     assign FCLK1 = FCLK[1];
     assign IRQF2P[0] = IRQ_F2P_0;

examples/pwm/ipcores/litex_pwm.yml

@@ -12,7 +12,7 @@ s_axi:
     in:
       AWADDR: [axi_awaddr, 31, 0]
       AWVALID: axi_awvalid
-      WDATA: [axi_wdata, 31, 0] 
+      WDATA: [axi_wdata, 31, 0]
       WSTRB: [axi_wstrb, 3, 0]
       WVALID: axi_wvalid
       BREADY: axi_bready

examples/pwm/sources/ps7.v

@@ -45,7 +45,7 @@ module ps7_inst (
     output         MAXIGP0WVALID
 );
     wire [ 3: 0] FCLK;
-    
+
     assign FCLK0 = FCLK[0];
 
     PS7 ps7 (

fpga_topwrap/templates/ipcore_desc.j2.yml

@@ -4,11 +4,11 @@
   {{name}}: {{value}}{%- endif -%}{%-endfor%}{% endif %}
 
 signals:
-  {% if ports['in'] %}in:{% for port in ports['in'] %}  
+  {% if ports['in'] %}in:{% for port in ports['in'] %}
     - {% if port.bounds[0] != port.bounds[1] %}[{{port.name}}, {{port.bounds[0]}}, {{port.bounds[1]}}]{% else %}{{port.name}}{% endif %}{%endfor%}{% endif %}
-  {% if ports['out'] %}out:{% for port in ports['out'] %}  
+  {% if ports['out'] %}out:{% for port in ports['out'] %}
     - {% if port.bounds[0] != port.bounds[1] %}[{{port.name}}, {{port.bounds[0]}}, {{port.bounds[1]}}]{% else %}{{port.name}}{% endif %}{%endfor%}{% endif %}
-  {% if ports['inout'] %}inout:{% for port in ports['inout'] %}  
+  {% if ports['inout'] %}inout:{% for port in ports['inout'] %}
     - {% if port.bounds[0] != port.bounds[1] %}[{{port.name}}, {{port.bounds[0]}}, {{port.bounds[1]}}]{% else %}{{port.name}}{% endif %}{%endfor%}{% endif %}
 {% for iface_name, iface in interfaces.items() %}
 {{iface_name}}:
@@ -17,6 +17,6 @@ signals:
       - {% if port.bounds[0] != port.bounds[1] %}[{{port.name}}, {{port.bounds[0]}}, {{port.bounds[1]}}]{% else %}{{port.name}}{% endif %}{%endfor%}{% endif %}
     {% if iface['out'] %}out:{% for port in iface['out'] %}
       - {% if port.bounds[0] != port.bounds[1] %}[{{port.name}}, {{port.bounds[0]}}, {{port.bounds[1]}}]{% else %}{{port.name}}{% endif %}{%endfor%}{% endif %}
-    {% if iface['inout'] %}inout:{% for port in iface['inout'] %}  
+    {% if iface['inout'] %}inout:{% for port in iface['inout'] %}
       - {% if port.bounds[0] != port.bounds[1] %}[{{port.name}}, {{port.bounds[0]}}, {{port.bounds[1]}}]{% else %}{{port.name}}{% endif %}{%endfor%}{% endif %}
 {%endfor%}

requirements.txt

@@ -1,10 +1,10 @@
-PyYaml
-click
+
+-r impl.requirements.txt
 amaranth-yosys
+click
 git+https://github.com/amaranth-lang/amaranth
-wasmtime==1.0.1
-numexpr
-hdlConvertor
 git+https://github.com/antmicro/kenning-pipeline-manager-backend-communication.git
-
--r impl.requirements.txt
+hdlConvertor
+numexpr
+PyYaml
+wasmtime==1.0.1

tests/data/axi_dispctrl_v1_0.vhd

@@ -321,10 +321,10 @@ axi_dispctrl_v1_0_S00_AXI_inst : axi_dispctrl_v1_0_S00_AXI
 		end if;
 	end process;
 
-Inst_vdma_to_vga: vdma_to_vga 
+Inst_vdma_to_vga: vdma_to_vga
 	GENERIC MAP(
 		C_S_AXIS_TDATA_WIDTH => C_S_AXIS_TDATA_WIDTH
-	)  
+	)
 	PORT MAP(
 		LOCKED_I => locked,
 		ENABLE_I => enable_reg,

tests/data/seg7_4d_ctrl.v

@@ -431,7 +431,7 @@ module seg7_4d_ctrl #(
     input wire dec_e,           // enable decimal format
     input wire sign_e,          // enable signed format
     input wire [15:0] d,        // input data
-    input wire [1:0] dpn,       // decimal point position 
+    input wire [1:0] dpn,       // decimal point position
     output wire [0:6] seg,      // 7-segment output
     output wire [3:0] select,   // select output (controls common anode/cathode)
     output wire dp              // decimal point output vector
@@ -488,12 +488,12 @@ module seg7_4d_ctrl #(
                 d_in = d;
         end
     end
-    
+
     // Calculate decimal point vector
     always @* begin
         dp_in = 'b0;
         dp_in[dpn] = dpn == 2'd0 ? 1'b0 : 1'b1;
-    end 
+    end
 
     // binary to bcd converter
     bin_to_bcd_14 bin_to_bcd_14 (
@@ -560,4 +560,3 @@ module seg7_4d_ctrl_test #(
         .dp(dp)
     );
 endmodule // seg7_4d_ctrl_test
-