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Introduce trait to avoid matching concrete subclass
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nvollmar committed Feb 21, 2024
1 parent 49d7b91 commit d7b7174
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Showing 3 changed files with 17 additions and 5 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -59,8 +59,8 @@ class DefaultFailureDetectorRegistry[A](detectorFactory: () => FailureDetector)

// address below was introduced as a var because of binary compatibility constraints
newDetector match {
case phi: PhiAccrualFailureDetector => phi.address = resource.toString
case _ =>
case dwa: FailureDetectorWithAddress => dwa.address = resource.toString
case _ =>
}

newDetector.heartbeat()
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Original file line number Diff line number Diff line change
Expand Up @@ -40,6 +40,16 @@ trait FailureDetector {

}

trait FailureDetectorWithAddress {

/**
* Address of observed host will be set after detector creation.
*/
def address_=(addr: String): Unit

private[pekko] def address: String
}

object FailureDetector {

/**
Expand All @@ -50,6 +60,6 @@ object FailureDetector {
abstract class Clock extends (() => Long)

implicit val defaultClock: Clock = new Clock {
def apply() = NANOSECONDS.toMillis(System.nanoTime)
def apply(): Long = NANOSECONDS.toMillis(System.nanoTime)
}
}
Original file line number Diff line number Diff line change
Expand Up @@ -73,7 +73,7 @@ class PhiAccrualFailureDetector(
eventStream: Option[EventStream])(
implicit
clock: Clock)
extends FailureDetector {
extends FailureDetector with FailureDetectorWithAddress {

/**
* Constructor without eventStream to support backwards compatibility
Expand Down Expand Up @@ -118,8 +118,10 @@ class PhiAccrualFailureDetector(

private val acceptableHeartbeatPauseMillis = acceptableHeartbeatPause.toMillis

def address_=(addr: String): Unit = this._address = addr
private[pekko] def address: String = this._address
// address below was introduced as a var because of binary compatibility constraints
private[pekko] var address: String = "N/A"
private var _address: String = "N/A"

/**
* Implement using optimistic lockless concurrency, all state is represented
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