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This repository contains the implementation of single cycle processor based on RISC-V ISA and implemented on "LOGISIM".

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arhamhashmi01/RV32I_Single_Cycle

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RISC-V Single Cycle Processor Implementation.

This repository contains the implementation of a single cycle processor based on the RISC-V ISA. The processor is designed and implemented in two different environments: Logisim and Verilog.

Features

RISC-V ISA: This processor is built to support the RISC-V instruction set architecture, a popular and open standard for instruction set architectures.

Single Cycle Design: The processor follows a single cycle design, making it a simple and educational platform for understanding the principles of processor architecture.

Logisim Implementation: You can explore the processor's functionality and logic in Logisim, a popular educational tool for simulating digital circuits.

Verilog Implementation: For those looking to implement the processor on hardware or in a more realistic setting, a Verilog version is also provided.

Getting Started

To get started with this processor, check out the respective folders for Logisim and Verilog implementations.