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lines changed Original file line number Diff line number Diff line change @@ -55,6 +55,9 @@ macro_rules! add_usart_spi {
5555 fn raw_setup( & mut self , settings: & $crate:: spi:: Settings ) {
5656 use $crate:: hal:: spi;
5757
58+ // UBRRn must be zero at the time the transmitter is enabled.
59+ self . [ <ubrr $n>] . write( |w| unsafe { w. bits( 0 ) } ) ;
60+
5861 // We have to translate the character size register into the 2 bits which are the MSB/LSB and the phase
5962 // 5 Bit Char = MSB and 1st
6063 // 6 Bit Char = MSB and 2nd
@@ -80,13 +83,14 @@ macro_rules! add_usart_spi {
8083 }
8184 } ) ;
8285
83- // Enable receiver and transmitter, and also the rec interrupt .
86+ // Enable receiver and transmitter.
8487 self . [ <ucsr $n b>] . write( |w| w
8588 . [ <txen $n>] ( ) . set_bit( )
8689 . [ <rxen $n>] ( ) . set_bit( )
8790 ) ;
8891
8992 // Set the clock divider for SPI clock.
93+ // This must be done after the transmitter is enabled.
9094 self . [ <ubrr $n>] . write( |w| {
9195 match settings. clock {
9296 $crate:: spi:: SerialClockRate :: OscfOver2 => w. bits( 0 ) ,
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