RISC-V Single-Cycle Processor

This repository contains the VHDL implementation of a single-cycle RISC-V processor. The design includes functional, behavioural, and RTL models. This project was completed by a team of four members.

University

Technical University of Munich

Team Members

• Arun Prema Murugavel
• Hian Zing Voon
• Tiemo Schmidt
• Yu-Hung Tsai