Pinned Loading

1. RISC-V-Processor RISC-V-Processor Public

   Verilog implementation of multi-stage 32-bit RISC-V processor

   Verilog 160 43

2. branch_predictor_simulator branch_predictor_simulator Public

   C++ Simulator modeling a gshare, bimodal and hybrid branch predictor

   C++

3. cache_simulator cache_simulator Public

   Configurable cache simulator with prefetch buffer. Capable of multilevel cache simulation.

   C++

4. superscalar_OOO_Processor_simulator superscalar_OOO_Processor_simulator Public

   C++ Simulator modeling superscalar out of order processor

   C++