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clk: combine regmap_* and regmap_mux_* operations
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Abstract a set of regmap_* operations by combining mux-specific ones and ordinary ones

Signed-off-by: Terry Bai <terry.z.bai@gmail.com>
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@terryzbai
terryzbai committed Nov 18, 2024
1 parent 0a6c664 commit d8a400c
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Showing 8 changed files with 79 additions and 101 deletions.
17 changes: 9 additions & 8 deletions drivers/clk/clk-operations.c
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Original file line number Diff line number Diff line change
Expand Up @@ -82,19 +82,20 @@
#include <clk-operations.h>
#include <sddf/timer/client.h>
#include <sddf/util/printf.h>
#include <clk_utils.h>

static inline int clk_gate_enable(struct clk *clk)
{
struct clk_gate_data *data = (struct clk_gate_data *)(clk->data);

return regmap_update_bits(clk->base, data->offset, data->bit_idx, 1, 1);
return regmap_update_bits(clk->base, data->offset, data->bit_idx, MASK(1), 1);
}

static inline int clk_gate_disable(struct clk *clk)
{
struct clk_gate_data *data = (struct clk_gate_data *)(clk->data);

regmap_update_bits(clk->base, data->offset, data->bit_idx, 1, 0);
regmap_update_bits(clk->base, data->offset, data->bit_idx, MASK(1), 0);
return 0;
}

Expand All @@ -109,7 +110,7 @@ static inline int clk_gate_is_enabled(struct clk *clk)
/* val &= BIT(gate->bit_idx); */
/* return val ? 1 : 0; */

return regmap_read_bits(clk->base, data->offset, data->bit_idx, 1);
return regmap_read_bits(clk->base, data->offset, data->bit_idx, MASK(1));
}

const struct clk_ops clk_gate_ops = {
Expand All @@ -126,7 +127,7 @@ static inline uint64_t clk_div_recalc_rate(const struct clk *clk, uint64_t prate
{

struct clk_div_data *data = (struct clk_div_data *)(clk->data);
uint32_t div = regmap_read_bits(clk->base, data->offset, data->shift, data->width);
uint32_t div = regmap_read_bits(clk->base, data->offset, data->shift, MASK(data->width));

/* TODO: Need to verify the following cases */
if (data->flags & CLK_DIVIDER_ONE_BASED) {
Expand Down Expand Up @@ -157,7 +158,7 @@ static inline int clk_div_set_rate(const struct clk *clk, uint64_t rate, uint64_
} else {
div -= 1;
}
return regmap_update_bits(clk->base, data->offset, data->shift, data->width, div);
return regmap_update_bits(clk->base, data->offset, data->shift, MASK(data->width), div);
}

const struct clk_ops clk_divider_ops = {
Expand All @@ -176,7 +177,7 @@ static inline uint8_t clk_mux_get_parent(const struct clk *clk)
{
struct clk_mux_data *data = (struct clk_mux_data *)(clk->data);
uint32_t num_parents = clk->hw.init->num_parents;
uint32_t val = regmap_mux_read_bits(clk->base, data->offset, data->shift, data->mask);
uint32_t val = regmap_read_bits(clk->base, data->offset, data->shift, data->mask);

if (data->table) {
int i;
Expand Down Expand Up @@ -208,9 +209,9 @@ static inline int clk_mux_set_parent(struct clk *clk, uint8_t index)

if (data->table) {
uint32_t val = data->table[index];
regmap_mux_update_bits(clk->base, data->offset, data->shift, data->mask, val);
regmap_update_bits(clk->base, data->offset, data->shift, data->mask, val);
}
regmap_mux_update_bits(clk->base, data->offset, data->shift, data->mask, index);
regmap_update_bits(clk->base, data->offset, data->shift, data->mask, index);

return 0;
}
Expand Down
30 changes: 3 additions & 27 deletions drivers/clk/clk-operations.h
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
#pragma once

#include <clk.h>
#include <utils.h>
#include <clk_utils.h>

#define CLK_INCORRECT_ARGS -1
#define CLK_INVALID_OP -2
Expand All @@ -22,31 +22,7 @@ static inline int reg_write(uint64_t base, uint32_t offset, uint32_t val)
return 0;
}

static inline int regmap_update_bits(uint64_t base, uint32_t offset, uint8_t shift, uint8_t width, uint32_t val)
{
volatile uint32_t *clk_reg = ((void *)base + offset);
uint32_t reg_val = *clk_reg;

reg_val &= ~(MASK(width) << shift);
reg_val |= ((MASK(width) & val) << shift);

*clk_reg = reg_val;

return 0;
}

static inline uint32_t regmap_read_bits(uint64_t base, uint32_t offset, uint8_t shift, uint8_t width)
{
volatile uint32_t *clk_reg = ((void *)base + offset);
uint32_t reg_val = *clk_reg;

reg_val >>= shift;
reg_val &= MASK(width);

return reg_val;
}

static inline int regmap_mux_update_bits(uint64_t base, uint32_t offset, uint8_t shift, uint32_t mask, uint32_t val)
static inline int regmap_update_bits(uint64_t base, uint32_t offset, uint8_t shift, uint32_t mask, uint32_t val)
{
volatile uint32_t *clk_reg = ((void *)base + offset);
uint32_t reg_val = *clk_reg;
Expand All @@ -59,7 +35,7 @@ static inline int regmap_mux_update_bits(uint64_t base, uint32_t offset, uint8_t
return 0;
}

static inline uint32_t regmap_mux_read_bits(uint64_t base, uint32_t offset, uint8_t shift, uint32_t mask)
static inline uint32_t regmap_read_bits(uint64_t base, uint32_t offset, uint8_t shift, uint32_t mask)
{
volatile uint32_t *clk_reg = ((void *)base + offset);
uint32_t reg_val = *clk_reg;
Expand Down
0 drivers/clk/utils.h → drivers/clk/clk_utils.h
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File renamed without changes.
60 changes: 30 additions & 30 deletions drivers/clk/imx/clk-imx.c
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Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@
* cfaaa7d010d1fc58f9717fcc8591201e741d2d49/drivers/clk/imx/clk-composite-8m.c
*/

#include <utils.h>
#include <clk_utils.h>
#include <clk-operations.h>
#include <clk-imx.h>

Expand All @@ -42,21 +42,21 @@ static int clk_gate2_enable(struct clk *clk)
{
struct clk_gate_data *data = (struct clk_gate_data *)(clk->data);

return regmap_update_bits(clk->base, data->offset, data->bit_idx, 2, 0x3);
return regmap_update_bits(clk->base, data->offset, data->bit_idx, MASK(2), 0x3);
}

static int clk_gate2_disable(struct clk *clk)
{
struct clk_gate_data *data = (struct clk_gate_data *)(clk->data);

return regmap_update_bits(clk->base, data->offset, data->bit_idx, 2, 0);
return regmap_update_bits(clk->base, data->offset, data->bit_idx, MASK(2), 0);
}

static int clk_gate2_is_enabled(struct clk *clk)
{
struct clk_gate_data *data = (struct clk_gate_data *)(clk->data);

if (regmap_read_bits(clk->base, data->offset, data->bit_idx, 2) == 0x3)
if (regmap_read_bits(clk->base, data->offset, data->bit_idx, MASK(2)) == 0x3)
return 1;

return 0;
Expand All @@ -78,14 +78,14 @@ static uint64_t clk_pll_recalc_rate(const struct clk *clk, uint64_t prate)
uint64_t rate;

/* Output Divider value is (n + 1) * 2 */
uint32_t output_div_val = regmap_read_bits(clk->base, data->offset, 0, 5);
uint32_t output_div_val = regmap_read_bits(clk->base, data->offset, 0, MASK(5));
output_div_val = (output_div_val + 1) * 2;

/* Valid Frac Divider value is 1 to 2^24 */
uint32_t frac_div_val = regmap_read_bits(clk->base, data->offset + 0x4, 7, 24);
uint32_t frac_div_val = regmap_read_bits(clk->base, data->offset + 0x4, 7, MASK(24));

/* Valid Int Divider value is 1 to 32 */
uint32_t int_div_val = regmap_read_bits(clk->base, data->offset + 0x4, 0, 7);
uint32_t int_div_val = regmap_read_bits(clk->base, data->offset + 0x4, 0, MASK(7));

temp_rate *= prate;
temp_rate *= frac_div_val;
Expand Down Expand Up @@ -114,15 +114,15 @@ static uint64_t clk_sscg_pll_recalc_rate(const struct clk *clk, uint64_t prate)
struct clk_sscg_pll_data *data = (struct clk_sscg_pll_data *)(clk->data);
uint64_t temp_rate = prate;

uint32_t divr1 = regmap_read_bits(clk->base, data->offset + 0x8, 25, 3);
uint32_t divr2 = regmap_read_bits(clk->base, data->offset + 0x8, 19, 6);
uint32_t divf1 = regmap_read_bits(clk->base, data->offset + 0x8, 13, 6);
uint32_t divf2 = regmap_read_bits(clk->base, data->offset + 0x8, 7, 6);
uint32_t divq = regmap_read_bits(clk->base, data->offset + 0x8, 1, 6);
uint32_t divr1 = regmap_read_bits(clk->base, data->offset + 0x8, 25, MASK(3));
uint32_t divr2 = regmap_read_bits(clk->base, data->offset + 0x8, 19, MASK(6));
uint32_t divf1 = regmap_read_bits(clk->base, data->offset + 0x8, 13, MASK(6));
uint32_t divf2 = regmap_read_bits(clk->base, data->offset + 0x8, 7, MASK(6));
uint32_t divq = regmap_read_bits(clk->base, data->offset + 0x8, 1, MASK(6));

if (regmap_read_bits(clk->base, data->offset, 4, 1)) {
if (regmap_read_bits(clk->base, data->offset, 4, MASK(1))) {
temp_rate = prate;
} else if (regmap_read_bits(clk->base, data->offset, 5, 1)) {
} else if (regmap_read_bits(clk->base, data->offset, 5, MASK(1))) {
temp_rate *= divf2;
do_div(temp_rate, (divr2 + 1) * (divq + 1));
} else {
Expand All @@ -139,9 +139,9 @@ static uint8_t clk_sscg_pll_get_parent(const struct clk *clk)
struct clk_sscg_pll_data *data = (struct clk_sscg_pll_data *)(clk->data);
uint8_t ret = 0;

if (regmap_read_bits(clk->base, data->offset, 4, 1)) {
if (regmap_read_bits(clk->base, data->offset, 4, MASK(1))) {
ret = data->bypass2;
} else if (regmap_read_bits(clk->base, data->offset, 5, 1)) {
} else if (regmap_read_bits(clk->base, data->offset, 5, MASK(1))) {
ret = data->bypass1;
}

Expand Down Expand Up @@ -173,7 +173,7 @@ static uint64_t imx8m_clk_core_slice_recalc_rate(const struct clk *clk, uint64_t
{
struct clk_core_slice_data *data = (struct clk_core_slice_data *)(clk->data);

uint32_t div_val = regmap_read_bits(clk->base, data->offset, data->div_shift, data->div_width);
uint32_t div_val = regmap_read_bits(clk->base, data->offset, data->div_shift, MASK(data->div_width));
/* Divider value is n+1 */
return DIV_ROUND_UP_ULL((uint64_t)prate, div_val + 1);
}
Expand All @@ -183,7 +183,7 @@ static uint8_t imx8m_clk_core_slice_get_parent(const struct clk *clk)
struct clk_core_slice_data *data = (struct clk_core_slice_data *)(clk->data);

uint32_t num_parents = clk->hw.init->num_parents;
uint32_t val = regmap_mux_read_bits(clk->base, data->offset, data->mux_shift, data->mux_mask);
uint32_t val = regmap_read_bits(clk->base, data->offset, data->mux_shift, data->mux_mask);

if (val >= num_parents)
return -1;
Expand All @@ -199,8 +199,8 @@ static int imx8m_clk_core_slice_set_parent(struct clk *clk, uint8_t index)
* write twice to make sure non-target interface
* SEL_A/B point the same clk input.
*/
regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index);
regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index);
regmap_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index);
regmap_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index);

return 0;
}
Expand All @@ -218,11 +218,11 @@ static uint64_t imx8m_clk_common_slice_recalc_rate(const struct clk *clk, uint64
{
struct clk_common_slice_data *data = (struct clk_common_slice_data *)(clk->data);

uint32_t prediv_val = regmap_read_bits(clk->base, data->offset, data->prevdiv_shift, data->prevdiv_width);
uint32_t prediv_val = regmap_read_bits(clk->base, data->offset, data->prevdiv_shift, MASK(data->prevdiv_width));
/* Divider value is n+1 */
uint64_t prediv_rate = DIV_ROUND_UP_ULL((uint64_t)prate, prediv_val + 1);

uint32_t postdiv_val = regmap_read_bits(clk->base, data->offset, data->postdiv_shift, data->postdiv_width);
uint32_t postdiv_val = regmap_read_bits(clk->base, data->offset, data->postdiv_shift, MASK(data->postdiv_width));
/* Divider value is n+1 */
return DIV_ROUND_UP_ULL((uint64_t)prediv_rate, postdiv_val + 1);
}
Expand All @@ -232,7 +232,7 @@ static uint8_t imx8m_clk_common_slice_get_parent(const struct clk *clk)
struct clk_common_slice_data *data = (struct clk_common_slice_data *)(clk->data);

uint32_t num_parents = clk->hw.init->num_parents;
uint32_t val = regmap_mux_read_bits(clk->base, data->offset, data->mux_shift, data->mux_mask);
uint32_t val = regmap_read_bits(clk->base, data->offset, data->mux_shift, data->mux_mask);

if (val >= num_parents)
return -1;
Expand All @@ -248,8 +248,8 @@ static int imx8m_clk_common_slice_set_parent(struct clk *clk, uint8_t index)
* write twice to make sure non-target interface
* SEL_A/B point the same clk input.
*/
regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index);
regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index);
regmap_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index);
regmap_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index);

return 0;
}
Expand All @@ -267,11 +267,11 @@ static uint64_t imx8m_clk_bus_slice_recalc_rate(const struct clk *clk, uint64_t
{
struct clk_bus_slice_data *data = (struct clk_bus_slice_data *)(clk->data);

uint32_t prediv_val = regmap_read_bits(clk->base, data->offset, data->prevdiv_shift, data->prevdiv_width);
uint32_t prediv_val = regmap_read_bits(clk->base, data->offset, data->prevdiv_shift, MASK(data->prevdiv_width));
/* Divider value is n+1 */
uint64_t prediv_rate = DIV_ROUND_UP_ULL((uint64_t)prate, prediv_val + 1);

uint32_t postdiv_val = regmap_read_bits(clk->base, data->offset, data->postdiv_shift, data->postdiv_width);
uint32_t postdiv_val = regmap_read_bits(clk->base, data->offset, data->postdiv_shift, MASK(data->postdiv_width));
/* Divider value is n+1 */
return DIV_ROUND_UP_ULL((uint64_t)prediv_rate, postdiv_val + 1);
}
Expand All @@ -281,7 +281,7 @@ static uint8_t imx8m_clk_bus_slice_get_parent(const struct clk *clk)
struct clk_bus_slice_data *data = (struct clk_bus_slice_data *)(clk->data);

uint32_t num_parents = clk->hw.init->num_parents;
uint32_t val = regmap_mux_read_bits(clk->base, data->offset, data->mux_shift, data->mux_mask);
uint32_t val = regmap_read_bits(clk->base, data->offset, data->mux_shift, data->mux_mask);

if (val >= num_parents)
return -1;
Expand All @@ -297,8 +297,8 @@ static int imx8m_clk_bus_slice_set_parent(struct clk *clk, uint8_t index)
* write twice to make sure non-target interface
* SEL_A/B point the same clk input.
*/
regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index);
regmap_mux_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index);
regmap_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index);
regmap_update_bits(clk->base, data->offset, data->mux_shift, data->mux_mask, index);

return 0;
}
Expand Down
2 changes: 1 addition & 1 deletion drivers/clk/imx/clk-imx8mq.c
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
*/

#include <clk.h>
#include <utils.h>
#include <clk_utils.h>
#include <imx8mq-bindings.h>
#include <clk-imx.h>
#include <sddf/util/util.h>
Expand Down
2 changes: 1 addition & 1 deletion drivers/clk/meson/clk-measure.c
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Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@

#include <clk-measure.h>
#include <clk-operations.h>
#include <utils.h>
#include <clk_utils.h>
#include <sddf/util/printf.h>
#include <sddf/timer/client.h>

Expand Down
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