32-Bit-ALU-Design

This project is a 32-bit Arithmetic Logic Unit (ALU) designed in SystemVerilog as part of a MIPS microprocessor simulation. The ALU supports various arithmetic and logical operations and includes a custom-built 32-bit full adder, one 2-to-1 MUX, one 4-to-1 MUX, one AND gate , one OR gate and the Zero Extend Logic

Author

• Arda Baran

  Features

• 32-bit arithmetic and logic operations

• One 32-bit full adder for efficient design

• Modular design using multiplexers for operation selection

• Zero-detection output