Update cn0540 spi engine (analogdevicesinc#1207)

Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>
bia1708 · Apr 5, 2024 · 92f8b30 · 92f8b30
1 parent 2ac95ba
commit 92f8b30
Show file tree

Hide file tree

Showing 7 changed files with 69 additions and 83 deletions.
diff --git a/projects/cn0540/common/cn0540_ardz.txt b/projects/cn0540/common/cn0540_ardz.txt
@@ -0,0 +1,35 @@
+Pin            Port               Schematic_name     System_top_name        IOSTANDARD  Termination
+
+# cn0540
+
+P3_5           CK_IO13            SCLK               cn0540_spi_sclk        LVCMOS33    IOB TRUE
+P3_6           CK_IO12            DOUT_RDYB          cn0540_spi_miso        LVCMOS33    IOB TRUE PULLTYPE PULLUP
+P3_7           CK_IO11            SDI                cn0540_spi_mosi        LVCMOS33    IOB TRUE PULLTYPE PULLUP
+P3_8           CK_IO10            CS_ADC             cn0540_spi_cs          LVCMOS33    IOB TRUE
+P3_9           CK_IO9             SHUTDOWN           cn0540_shutdown        LVCMOS33    #N/A
+P5_1           CK_IO7             RESET_ADC          cn0540_reset_adc       LVCMOS33    #N/A
+P5_3           CK_IO5             CSB_AUX            cn0540_csb_aux         LVCMOS33    #N/A
+P5_4           CK_IO4             SW_FF              cn0540_sw_ff           LVCMOS33    #N/A
+P5_5           CK_IO3             DRDY_AUX           cn0540_drdy_aux        LVCMOS33    #N/A  
+P5_7           CK_IO1             BLUE_LED           cn0540_blue_led        LVCMOS33    #N/A  
+P5_8           CK_IO0             RED_LED            cn0540_yellow_led      LVCMOS33    #N/A
+P5_2           CK_IO6             SYMC_IN            cn0540_sync_in         LVCMOS33    #N/A
+P5_6           CK_IO2             DRDY               cn0540_drdy            LVCMOS33    #N/A
+P3_1           CK_SCL             SCL                cn0540_scl             LVCMOS33    #N/A
+P3_2           CK_SDA             SDA                cn0540_sda             LVCMOS33    #N/A   
+
+NC             XADC_V_P           NC                 cn0540_xadc_mux_p      LVCMOS33    #N/A
+NC             XADC_V_N           NC                 cn0540_xadc_mux_n      LVCMOS33    #N/A
+
+P4_1           CK_AN0_P           IO5                cn0540_ck_an0_p        LVCMOS33    #N/A     
+NC             CK_AN0_N           GND                cn0540_ck_an0_n        LVCMOS33    #N/A
+P4_2           CK_AN1_P           IO4                cn0540_ck_an1_p        LVCMOS33    #N/A 
+NC             CK_AN1_N           GND                cn0540_ck_an1_n        LVCMOS33    #N/A
+P4_3           CK_AN2_P           IO3                cn0540_ck_an2_p        LVCMOS33    #N/A
+NC             CK_AN2_N           GND                cn0540_ck_an2_n        LVCMOS33    #N/A
+P4_4           CK_AN3_P           NC                 cn0540_ck_an3_p        LVCMOS33    #N/A
+NC             CK_AN3_N           GND                cn0540_ck_an3_n        LVCMOS33    #N/A
+P4_5           CK_AN4_P           NC                 cn0540_ck_an4_p        LVCMOS33    #N/A
+NC             CK_AN4_N           GND                cn0540_ck_an4_n        LVCMOS33    #N/A
+P4_6           CK_AN5_P           IO0                cn0540_ck_an5_p        LVCMOS33    #N/A
+NC             CK_AN5_N           GND                cn0540_ck_an5_n        LVCMOS33    #N/A
diff --git a/projects/cn0540/common/cn0540_bd.tcl b/projects/cn0540/common/cn0540_bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -15,6 +15,19 @@ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.
 
 create_bd_port -dir I adc_data_ready
 
+source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
+
+set data_width    32
+set async_spi_clk 1
+set num_cs        1
+set num_sdi       1
+set num_sdo       1
+set sdi_delay     0
+set echo_sclk     0
+
+set hier_spi_engine spi_cn0540
+
+spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
 
 ad_ip_instance axi_iic axi_iic_cn0540
 ad_connect iic_cn0540 axi_iic_cn0540/iic
@@ -25,69 +38,6 @@ ad_ip_instance axi_clkgen spi_clkgen
 ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 10
 ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1
 ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 8
-ad_connect $sys_cpu_clk spi_clkgen/clk
-ad_connect spi_clk spi_clkgen/clk_0
-
-# create a SPI Engine architecture for ADC
-
-create_bd_cell -type hier spi_adc
-current_bd_instance /spi_adc
-
-  create_bd_pin -dir I -type clk clk
-  create_bd_pin -dir I -type clk spi_clk
-  create_bd_pin -dir I -type rst resetn
-  create_bd_pin -dir I drdy
-  create_bd_pin -dir O irq
-  create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
-  create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE
-
-  # DATA_WIDTH is set to 32
-
-  ad_ip_instance spi_engine_execution execution
-  ad_ip_parameter execution CONFIG.DATA_WIDTH 32
-  ad_ip_parameter execution CONFIG.NUM_OF_CS 1
-
-  ad_ip_instance axi_spi_engine axi_regmap
-  ad_ip_parameter axi_regmap CONFIG.DATA_WIDTH 32
-  ad_ip_parameter axi_regmap CONFIG.NUM_OFFLOAD 1
-  ad_ip_parameter axi_regmap CONFIG.ASYNC_SPI_CLK 1
-
-  ad_ip_instance spi_engine_offload offload
-  ad_ip_parameter offload CONFIG.DATA_WIDTH 32
-  ad_ip_parameter offload CONFIG.ASYNC_TRIG 1
-  ad_ip_parameter offload CONFIG.ASYNC_SPI_CLK 1
-
-  ad_ip_instance spi_engine_interconnect interconnect
-  ad_ip_parameter interconnect CONFIG.DATA_WIDTH 32
-
-  ad_connect axi_regmap/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl
-  ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl
-  ad_connect axi_regmap/spi_engine_ctrl interconnect/s1_ctrl
-  ad_connect interconnect/m_ctrl execution/ctrl
-  ad_connect offload/offload_sdi M_AXIS_SAMPLE
-
-  ad_connect execution/spi m_spi
-
-  ad_connect spi_clk offload/spi_clk
-  ad_connect spi_clk offload/ctrl_clk
-  ad_connect spi_clk execution/clk
-  ad_connect clk axi_regmap/s_axi_aclk
-  ad_connect spi_clk axi_regmap/spi_clk
-  ad_connect spi_clk interconnect/clk
-
-  ad_connect axi_regmap/spi_resetn offload/spi_resetn
-  ad_connect axi_regmap/spi_resetn execution/resetn
-  ad_connect axi_regmap/spi_resetn interconnect/resetn
-
-  ad_connect drdy offload/trigger
-
-  ad_connect resetn axi_regmap/s_axi_aresetn
-  ad_connect irq axi_regmap/irq
-
-
-current_bd_instance /
-
-ad_connect adc_data_ready spi_adc/drdy
 
 # dma for the ADC
 
@@ -102,13 +52,18 @@ ad_ip_parameter axi_cn0540_dma CONFIG.DMA_2D_TRANSFER 0
 ad_ip_parameter axi_cn0540_dma CONFIG.DMA_DATA_WIDTH_SRC 32
 ad_ip_parameter axi_cn0540_dma CONFIG.DMA_DATA_WIDTH_DEST 64
 
-ad_connect  $sys_cpu_clk spi_adc/clk
-ad_connect  $sys_cpu_resetn spi_adc/resetn
-ad_connect  $sys_cpu_resetn axi_cn0540_dma/m_dest_axi_aresetn
+ad_connect $sys_cpu_clk spi_clkgen/clk
+ad_connect spi_clk spi_clkgen/clk_0
 
-ad_connect  spi_adc/m_spi adc_spi
-ad_connect  spi_clk spi_adc/spi_clk
-ad_connect  axi_cn0540_dma/s_axis spi_adc/M_AXIS_SAMPLE
+ad_connect adc_data_ready $hier_spi_engine/trigger
+ad_connect axi_cn0540_dma/s_axis $hier_spi_engine/M_AXIS_SAMPLE
+ad_connect $hier_spi_engine/m_spi adc_spi
+
+ad_connect $sys_cpu_clk $hier_spi_engine/clk
+ad_connect spi_clk $hier_spi_engine/spi_clk
+ad_connect spi_clk axi_cn0540_dma/s_axis_aclk
+ad_connect sys_cpu_resetn $hier_spi_engine/resetn
+ad_connect sys_cpu_resetn axi_cn0540_dma/m_dest_axi_aresetn
 
 # Xilinx's XADC
 
@@ -143,19 +98,17 @@ ad_connect xadc_in/Vaux15 xadc_vaux15
 
 # AXI address definitions
 
-ad_cpu_interconnect 0x44a00000 spi_adc/axi_regmap
+ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
 ad_cpu_interconnect 0x44a30000 axi_cn0540_dma
 ad_cpu_interconnect 0x44a40000 axi_iic_cn0540
 ad_cpu_interconnect 0x44a50000 xadc_in
 ad_cpu_interconnect 0x44a70000 spi_clkgen
 
-ad_connect spi_clk axi_cn0540_dma/s_axis_aclk
-
 # interrupts
 
 ad_cpu_interrupt "ps-13" "mb-13" axi_cn0540_dma/irq
 ad_cpu_interrupt "ps-12" "mb-12" axi_iic_cn0540/iic2intc_irpt
-ad_cpu_interrupt "ps-11" "mb-11" spi_adc/irq
+ad_cpu_interrupt "ps-11" "mb-11" $hier_spi_engine/irq
 
 # memory interconnects
 

diff --git a/projects/cn0540/coraz7s/Makefile b/projects/cn0540/coraz7s/Makefile
@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################
@@ -11,6 +11,7 @@ M_DEPS += ../../scripts/adi_pd.tcl
 M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl
 M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc
 M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl
+M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl
 M_DEPS += ../../../library/common/ad_iobuf.v
 
 LIB_DEPS += axi_clkgen

diff --git a/projects/cn0540/coraz7s/system_bd.tcl b/projects/cn0540/coraz7s/system_bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -18,4 +18,3 @@ sysid_gen_sys_init_file
 set sys_dma_clk [get_bd_nets sys_dma_clk]
 
 source ../common/cn0540_bd.tcl
-
diff --git a/projects/cn0540/coraz7s/system_constr.xdc b/projects/cn0540/coraz7s/system_constr.xdc
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2020-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -8,7 +8,7 @@
 set_property -dict {PACKAGE_PIN  G15 IOSTANDARD LVCMOS33 IOB TRUE}                  [get_ports cn0540_spi_sclk]    ; ## CK_IO13
 set_property -dict {PACKAGE_PIN  J18 IOSTANDARD LVCMOS33 IOB TRUE PULLTYPE PULLUP}  [get_ports cn0540_spi_miso]    ; ## CK_IO12
 set_property -dict {PACKAGE_PIN  K18 IOSTANDARD LVCMOS33 IOB TRUE PULLTYPE PULLUP}  [get_ports cn0540_spi_mosi]    ; ## CK_IO11
-set_property -dict {PACKAGE_PIN  U15 IOSTANDARD LVCMOS33}                           [get_ports cn0540_spi_cs]      ; ## CK_IO10
+set_property -dict {PACKAGE_PIN  U15 IOSTANDARD LVCMOS33 IOB TRUE}                  [get_ports cn0540_spi_cs]      ; ## CK_IO10
 
 # reset and GPIO signals
 
@@ -57,4 +57,3 @@ set_property -dict { PACKAGE_PIN J20   IOSTANDARD LVCMOS33 } [get_ports { cn0540
 set_property -dict { PACKAGE_PIN H20   IOSTANDARD LVCMOS33 } [get_ports { cn0540_ck_an4_n }]; #IO_L17N_T2_AD5N_35 Sch=ck_an_n[4]
 set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports { cn0540_ck_an5_p }]; #IO_L18P_T2_AD13P_35 Sch=ck_an_p[5]
 set_property -dict { PACKAGE_PIN G20   IOSTANDARD LVCMOS33 } [get_ports { cn0540_ck_an5_n }]; #IO_L18N_T2_AD13N_35 Sch=ck_an_n[5]
-
diff --git a/projects/cn0540/coraz7s/system_project.tcl b/projects/cn0540/coraz7s/system_project.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2016-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -16,4 +16,3 @@ adi_project_files cn0540_coraz7s [list \
     "$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc"]
 
 adi_project_run cn0540_coraz7s
-
diff --git a/projects/cn0540/coraz7s/system_top.v b/projects/cn0540/coraz7s/system_top.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2020-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are