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prepare for release 0.0.2
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@recoules
recoules committed Apr 15, 2022
1 parent 0dc5cdd commit 6556a45
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Showing 53 changed files with 6,754 additions and 1,181 deletions.
5 changes: 5 additions & 0 deletions CHANGES.md
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Original file line number Diff line number Diff line change
@@ -1,3 +1,8 @@
## 0.0.2 (2022-04-15)

- handling of SSE instructions for AMD64
- various bug fixes and code generator improvements

## 0.0.1 (2022-03-14)

- update build system (dune 3.0) and improve dependency tracking
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308 changes: 117 additions & 191 deletions aarch32/decoder.cc
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48 changes: 24 additions & 24 deletions aarch64/aarch64dec.tcc
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Original file line number Diff line number Diff line change
Expand Up @@ -11566,7 +11566,7 @@ void OpLdarb_w< ARCH>::execute( ARCH & cpu)

U64 addr( cpu.GetGSR(rn) );
U8 data( cpu.MemRead8(addr) );
cpu.SetGZR(rt, data);
cpu.SetGZR(rt, typename ARCH::U32(data));
}}

template < typename ARCH>
Expand All @@ -11591,7 +11591,7 @@ void OpLdarh_w< ARCH>::execute( ARCH & cpu)

U64 addr( cpu.GetGSR(rn) );
U16 data( cpu.MemRead16(addr) );
cpu.SetGZR(rt, data);
cpu.SetGZR(rt, typename ARCH::U32(data));
}}

template < typename ARCH>
Expand Down Expand Up @@ -12217,7 +12217,7 @@ void OpLdrb_wxi< ARCH>::execute( ARCH & cpu)
U64 addr( cpu.GetGSR(rn) ), oaddr( addr + U64(imm) );
addr = (am == 1 ? addr : oaddr);
U8 data( cpu.MemRead8(addr) );
cpu.SetGZR(rt, data);
cpu.SetGZR(rt, typename ARCH::U32(data));
if (am & 1)
cpu.SetGSR(rn, oaddr);
}}
Expand All @@ -12244,7 +12244,7 @@ void OpLdrb_wuo< ARCH>::execute( ARCH & cpu)

U64 addr( cpu.GetGSR(rn) + U64(imm) );
U8 data( cpu.MemRead8(addr) );
cpu.SetGZR(rt, data);
cpu.SetGZR(rt, typename ARCH::U32(data));
}}

template < typename ARCH>
Expand Down Expand Up @@ -12373,7 +12373,7 @@ void OpLdrh_wxi< ARCH>::execute( ARCH & cpu)
U64 addr( cpu.GetGSR(rn) ), oaddr( addr + U64(imm) );
addr = (am == 1 ? addr : oaddr);
U16 data( cpu.MemRead16(addr) );
cpu.SetGZR(rt, data);
cpu.SetGZR(rt, typename ARCH::U32(data));
if (am & 1)
cpu.SetGSR(rn, oaddr );
}}
Expand All @@ -12400,7 +12400,7 @@ void OpLdrh_wuo< ARCH>::execute( ARCH & cpu)

U64 addr( cpu.GetGSR(rn) + U64(imm) );
U16 data( cpu.MemRead16(addr) );
cpu.SetGZR(rt, data);
cpu.SetGZR(rt, typename ARCH::U32(data));
}}

template < typename ARCH>
Expand Down Expand Up @@ -18198,7 +18198,7 @@ void OpCasb_w< ARCH>::execute( ARCH & cpu)

if (cpu.Test(data == comparevalue))
cpu.MemWrite8(addr, U8(cpu.GetGZR(rt)));
cpu.SetGZR(rs, data);
cpu.SetGZR(rs, typename ARCH::U32(data));
/*END ATOMIC*/
}}

Expand Down Expand Up @@ -18230,7 +18230,7 @@ void OpCash_w< ARCH>::execute( ARCH & cpu)

if (cpu.Test(data == comparevalue))
cpu.MemWrite16(addr, U16(cpu.GetGZR(rt)));
cpu.SetGZR(rs, data);
cpu.SetGZR(rs, typename ARCH::U32(data));
/*END ATOMIC*/
}}

Expand Down Expand Up @@ -18488,7 +18488,7 @@ void OpLdstaddb_w< ARCH>::execute( ARCH & cpu)
/*BEG ATOMIC*/
U8 oldval( cpu.MemRead8(addr) ), newval( oldval + U8(cpu.GetGZR(rs)) );
cpu.MemWrite8(addr, newval);
cpu.SetGZR(rt, oldval);
cpu.SetGZR(rt, typename ARCH::U32(oldval));
/*END ATOMIC*/;
}}

Expand Down Expand Up @@ -18521,7 +18521,7 @@ void OpLdstaddh_w< ARCH>::execute( ARCH & cpu)
/*BEG ATOMIC*/
U16 oldval( cpu.MemRead16(addr) ), newval( oldval + U16(cpu.GetGZR(rs)) );
cpu.MemWrite16(addr, newval);
cpu.SetGZR(rt, oldval);
cpu.SetGZR(rt, typename ARCH::U32(oldval));
/*END ATOMIC*/;
}}

Expand Down Expand Up @@ -18619,7 +18619,7 @@ void OpLdstclrb_w< ARCH>::execute( ARCH & cpu)
/*BEG ATOMIC*/
U8 oldval( cpu.MemRead8(addr) ), newval( oldval & ~U8(cpu.GetGZR(rs)) );
cpu.MemWrite8(addr, newval);
cpu.SetGZR(rt, oldval);
cpu.SetGZR(rt, typename ARCH::U32(oldval));
/*END ATOMIC*/;
}}

Expand Down Expand Up @@ -18652,7 +18652,7 @@ void OpLdstclrh_w< ARCH>::execute( ARCH & cpu)
/*BEG ATOMIC*/
U16 oldval( cpu.MemRead16(addr) ), newval( oldval & ~U16(cpu.GetGZR(rs)) );
cpu.MemWrite16(addr, newval);
cpu.SetGZR(rt, oldval);
cpu.SetGZR(rt, typename ARCH::U32(oldval));
/*END ATOMIC*/;
}}

Expand Down Expand Up @@ -18750,7 +18750,7 @@ void OpLdsteorb_w< ARCH>::execute( ARCH & cpu)
/*BEG ATOMIC*/
U8 oldval( cpu.MemRead8(addr) ), newval( oldval ^ U8(cpu.GetGZR(rs)) );
cpu.MemWrite8(addr, newval);
cpu.SetGZR(rt, oldval);
cpu.SetGZR(rt, typename ARCH::U32(oldval));
/*END ATOMIC*/;
}}

Expand Down Expand Up @@ -18783,7 +18783,7 @@ void OpLdsteorh_w< ARCH>::execute( ARCH & cpu)
/*BEG ATOMIC*/
U16 oldval( cpu.MemRead16(addr) ), newval( oldval ^ U16(cpu.GetGZR(rs)) );
cpu.MemWrite16(addr, newval);
cpu.SetGZR(rt, oldval);
cpu.SetGZR(rt, typename ARCH::U32(oldval));
/*END ATOMIC*/;
}}

Expand Down Expand Up @@ -18881,7 +18881,7 @@ void OpLdstsetb_w< ARCH>::execute( ARCH & cpu)
/*BEG ATOMIC*/
U8 oldval( cpu.MemRead8(addr) ), newval( oldval | U8(cpu.GetGZR(rs)) );
cpu.MemWrite8(addr, newval);
cpu.SetGZR(rt, oldval);
cpu.SetGZR(rt, typename ARCH::U32(oldval));
/*END ATOMIC*/;
}}

Expand Down Expand Up @@ -18914,7 +18914,7 @@ void OpLdstseth_w< ARCH>::execute( ARCH & cpu)
/*BEG ATOMIC*/
U16 oldval( cpu.MemRead16(addr) ), newval( oldval | U16(cpu.GetGZR(rs)) );
cpu.MemWrite16(addr, newval);
cpu.SetGZR(rt, oldval);
cpu.SetGZR(rt, typename ARCH::U32(oldval));
/*END ATOMIC*/;
}}

Expand Down Expand Up @@ -19015,7 +19015,7 @@ void OpLdstsmaxb_w< ARCH>::execute( ARCH & cpu)
/*BEG ATOMIC*/
U8 oldval( cpu.MemRead8(addr) ), newval( U8(Maximum(S8(oldval), S8(cpu.GetGZR(rs)))) );
cpu.MemWrite8(addr, newval);
cpu.SetGZR(rt, oldval);
cpu.SetGZR(rt, typename ARCH::U32(oldval));
/*END ATOMIC*/;
}}

Expand Down Expand Up @@ -19049,7 +19049,7 @@ void OpLdstsmaxh_w< ARCH>::execute( ARCH & cpu)
/*BEG ATOMIC*/
U16 oldval( cpu.MemRead16(addr) ), newval( U16(Maximum(S16(oldval), S16(cpu.GetGZR(rs)))) );
cpu.MemWrite16(addr, newval);
cpu.SetGZR(rt, oldval);
cpu.SetGZR(rt, typename ARCH::U32(oldval));
/*END ATOMIC*/;
}}

Expand Down Expand Up @@ -19150,7 +19150,7 @@ void OpLdstsminb_w< ARCH>::execute( ARCH & cpu)
/*BEG ATOMIC*/
U8 oldval( cpu.MemRead8(addr) ), newval( U8(Minimum(S8(oldval), S8(cpu.GetGZR(rs)))) );
cpu.MemWrite8(addr, newval);
cpu.SetGZR(rt, oldval);
cpu.SetGZR(rt, typename ARCH::U32(oldval));
/*END ATOMIC*/;
}}

Expand Down Expand Up @@ -19184,7 +19184,7 @@ void OpLdstsminh_w< ARCH>::execute( ARCH & cpu)
/*BEG ATOMIC*/
U16 oldval( cpu.MemRead16(addr) ), newval( U16(Minimum(S16(oldval), S16(cpu.GetGZR(rs)))) );
cpu.MemWrite16(addr, newval);
cpu.SetGZR(rt, oldval);
cpu.SetGZR(rt, typename ARCH::U32(oldval));
/*END ATOMIC*/;
}}

Expand Down Expand Up @@ -19282,7 +19282,7 @@ void OpLdstumaxb_w< ARCH>::execute( ARCH & cpu)
/*BEG ATOMIC*/
U8 oldval( cpu.MemRead8(addr) ), newval( Maximum(oldval, U8(cpu.GetGZR(rs))) );
cpu.MemWrite8(addr, newval);
cpu.SetGZR(rt, oldval);
cpu.SetGZR(rt, typename ARCH::U32(oldval));
/*END ATOMIC*/;
}}

Expand Down Expand Up @@ -19315,7 +19315,7 @@ void OpLdstumaxh_w< ARCH>::execute( ARCH & cpu)
/*BEG ATOMIC*/
U16 oldval( cpu.MemRead16(addr) ), newval( Maximum(oldval, U16(cpu.GetGZR(rs))) );
cpu.MemWrite16(addr, newval);
cpu.SetGZR(rt, oldval);
cpu.SetGZR(rt, typename ARCH::U32(oldval));
/*END ATOMIC*/;
}}

Expand Down Expand Up @@ -19413,7 +19413,7 @@ void OpLdstuminb_w< ARCH>::execute( ARCH & cpu)
/*BEG ATOMIC*/
U8 oldval( cpu.MemRead8(addr) ), newval( Minimum(oldval, U8(cpu.GetGZR(rs))) );
cpu.MemWrite8(addr, newval);
cpu.SetGZR(rt, oldval);
cpu.SetGZR(rt, typename ARCH::U32(oldval));
/*END ATOMIC*/;
}}

Expand Down Expand Up @@ -19446,7 +19446,7 @@ void OpLdstuminh_w< ARCH>::execute( ARCH & cpu)
/*BEG ATOMIC*/
U16 oldval( cpu.MemRead16(addr) ), newval( Minimum(oldval, U16(cpu.GetGZR(rs))) );
cpu.MemWrite16(addr, newval);
cpu.SetGZR(rt, oldval);
cpu.SetGZR(rt, typename ARCH::U32(oldval));
/*END ATOMIC*/;
}}

Expand Down
103 changes: 27 additions & 76 deletions aarch64/decoder.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -64,73 +64,14 @@ struct Processor

typedef unisim::util::symbolic::FP FP;
typedef unisim::util::symbolic::Expr Expr;
typedef unisim::util::symbolic::ScalarType ScalarType;
typedef unisim::util::symbolic::ValueType ValueType;
typedef unisim::util::symbolic::binsec::ActionNode ActionNode;

typedef unisim::util::symbolic::binsec::Store Store;
typedef unisim::util::symbolic::binsec::Load Load;
typedef unisim::util::symbolic::binsec::Branch Branch;

template <typename RID>
struct RegRead : public unisim::util::symbolic::binsec::RegRead
{
typedef RegRead<RID> this_type;
typedef unisim::util::symbolic::binsec::RegRead Super;
RegRead( RID _id, ScalarType::id_t _tp ) : Super(), tp(_tp), id(_id) {}
virtual this_type* Mutate() const override { return new this_type( *this ); }
virtual ScalarType::id_t GetType() const override { return tp; }
virtual void GetRegName( std::ostream& sink ) const override { sink << id.c_str(); }
virtual int cmp( ExprNode const& rhs ) const override { return compare( dynamic_cast<RegRead const&>( rhs ) ); }
int compare( RegRead const& rhs ) const { if (int delta = int(tp) - int(rhs.tp)) return delta; if (int delta = id.cmp( rhs.id )) return delta; return Super::compare(rhs); }
virtual Expr Simplify() const { return this; }

ScalarType::id_t tp;
RID id;
};

template <typename RID>
static Expr newRegRead( RID id, ScalarType::id_t tp ) { return new RegRead<RID>( id, tp ); }
static Expr newRegRead( RID id ) { return new unisim::util::symbolic::binsec::RegRead<RID>( id ); }

template <typename RID>
struct RegWrite : public unisim::util::symbolic::binsec::RegWrite
{
typedef RegWrite<RID> this_type;
typedef unisim::util::symbolic::binsec::RegWrite Super;
RegWrite( RID _id, Expr const& _value ) : Super(_value), id(_id) {}
virtual this_type* Mutate() const override { return new this_type( *this ); }

virtual void GetRegName( std::ostream& sink ) const override { sink << id.c_str(); }
virtual int cmp( ExprNode const& rhs ) const override { return compare( dynamic_cast<RegWrite const&>( rhs ) ); }
int compare( RegWrite const& rhs ) const { if (int delta = id.cmp( rhs.id )) return delta; return Super::cmp( rhs ); }
virtual Expr Simplify() const override
{
Expr nvalue( ASExprNode::Simplify( value ) );
return nvalue != value ? new RegWrite<RID>( id, nvalue ) : this;
}

RID id;
};

template <typename RID>
static RegWrite<RID>* newRegWrite( RID id, Expr const& value )
{ return new RegWrite<RID>( id, value ); }

struct Goto : public unisim::util::symbolic::binsec::Branch
{
Goto( Expr const& value ) : unisim::util::symbolic::binsec::Branch( value ) {}
virtual Goto* Mutate() const override { return new Goto( *this ); }
virtual void GetRegName( std::ostream& sink ) const override { sink << "pc"; }
virtual void annotate(std::ostream& sink) const override { return; }
};

struct Call : public Goto
{
Call( Expr const& value, uint32_t ra ) : Goto( value ), return_address( ra ) {}
virtual Call* Mutate() const override { return new Call( *this ); }
virtual void annotate(std::ostream& sink) const override { sink << " // call (" << unisim::util::symbolic::binsec::dbx(4,return_address) << ",0)"; }

uint32_t return_address;
};
static Expr newRegWrite( RID id, Expr const& value ) { return new unisim::util::symbolic::binsec::RegWrite<RID>( id, value ); }

// =====================================================================
// = Construction/Destruction =
Expand All @@ -153,19 +94,19 @@ struct Processor
, unpredictable( false )
{
for (GPR reg; reg.next();)
gpr[reg.idx()] = newRegRead(reg, ScalarType::U64);
gpr[reg.idx()] = newRegRead(reg);
for (Flag flag; flag.next();)
flags[flag.idx()] = newRegRead(flag, ScalarType::BOOL);
flags[flag.idx()] = newRegRead(flag);
}

bool
close( Processor const& ref, uint64_t linear_nia )
{
bool complete = path->close();
if (branch_type == B_CALL)
path->sinks.insert( Expr( new Call( next_instruction_address.expr, linear_nia ) ) );
path->sinks.insert( Expr( new unisim::util::symbolic::binsec::Call<uint64_t>( next_instruction_address.expr, linear_nia ) ) );
else
path->sinks.insert( Expr( new Goto( next_instruction_address.expr ) ) );
path->sinks.insert( Expr( new unisim::util::symbolic::binsec::Branch( next_instruction_address.expr ) ) );
if (unpredictable)
{
path->sinks.insert( Expr( new unisim::util::symbolic::binsec::AssertFalse() ) );
Expand Down Expand Up @@ -328,15 +269,15 @@ struct Processor
// = Memory access methods =
// =====================================================================

U64 MemRead64(U64 addr) { return U64( Expr( new Load( addr.expr, 8, 0, false ) ) ); }
U32 MemRead32(U64 addr) { return U32( Expr( new Load( addr.expr, 4, 0, false ) )); }
U16 MemRead16(U64 addr) { return U16( Expr( new Load( addr.expr, 2, 0, false ) ) ); }
U8 MemRead8 (U64 addr) { return U8 ( Expr( new Load( addr.expr, 1, 0, false ) ) ); }
U64 MemRead64(U64 addr) { return U64( Expr( new unisim::util::symbolic::binsec::Load( addr.expr, 8, 0, false ) ) ); }
U32 MemRead32(U64 addr) { return U32( Expr( new unisim::util::symbolic::binsec::Load( addr.expr, 4, 0, false ) ) ); }
U16 MemRead16(U64 addr) { return U16( Expr( new unisim::util::symbolic::binsec::Load( addr.expr, 2, 0, false ) ) ); }
U8 MemRead8 (U64 addr) { return U8 ( Expr( new unisim::util::symbolic::binsec::Load( addr.expr, 1, 0, false ) ) ); }

void MemWrite64(U64 addr, U64 value) { stores.insert( new Store( addr.expr, value.expr, 8, 0, false ) ); }
void MemWrite32(U64 addr, U32 value) { stores.insert( new Store( addr.expr, value.expr, 4, 0, false ) ); }
void MemWrite16(U64 addr, U16 value) { stores.insert( new Store( addr.expr, value.expr, 2, 0, false ) ); }
void MemWrite8 (U64 addr, U8 value) { stores.insert( new Store( addr.expr, value.expr, 1, 0, false ) ); }
void MemWrite64(U64 addr, U64 value) { stores.insert( new unisim::util::symbolic::binsec::Store( addr.expr, value.expr, 8, 0, false ) ); }
void MemWrite32(U64 addr, U32 value) { stores.insert( new unisim::util::symbolic::binsec::Store( addr.expr, value.expr, 4, 0, false ) ); }
void MemWrite16(U64 addr, U16 value) { stores.insert( new unisim::util::symbolic::binsec::Store( addr.expr, value.expr, 2, 0, false ) ); }
void MemWrite8 (U64 addr, U8 value) { stores.insert( new unisim::util::symbolic::binsec::Store( addr.expr, value.expr, 1, 0, false ) ); }

void ClearExclusiveLocal() { throw 0; }
void SetExclusiveMonitors( U64, unsigned size ) { throw 0; }
Expand All @@ -348,8 +289,11 @@ struct Processor
// = Processor Storage =
// =====================================================================

struct GPR : public unisim::util::identifier::Identifier<GPR>
struct GPR
: public unisim::util::identifier::Identifier<GPR>
, public unisim::util::symbolic::WithValueType<GPR>
{
typedef uint64_t value_type;
enum Code
{
x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15,
Expand All @@ -365,21 +309,28 @@ struct Processor
};
return names[int(code)];
}

void Repr(std::ostream& sink) const { sink << c_str(); }

GPR() : code(end) {}
GPR( Code _code ) : code(_code) {}
GPR( char const* _code ) : code(end) { init( _code ); }
};

struct Flag : public unisim::util::identifier::Identifier<Flag>
struct Flag
: public unisim::util::identifier::Identifier<Flag>
, unisim::util::symbolic::WithValueType<Flag>
{
typedef bool value_type;
enum Code { N, Z, C, V, end } code;

char const* c_str() const
{
static char const* names[] = {"n", "z", "c", "v", "NA"};
return names[int(code)];
}

void Repr(std::ostream& sink) const { sink << c_str(); }

Flag() : code(end) {}
Flag( Code _code ) : code(_code) {}
Expand Down
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