Add WGM bits and modes for Counter/Timer 0 in ATMega16 and ATMega32.

Patch by user GeorgKorger for Issue #538.
buserror · Nov 5, 2024 · 8d8e833 · 8d8e833
1 parent 132cc67
commit 8d8e833
Showing 1 changed file with 10 additions and 0 deletions.
diff --git a/simavr/cores/sim_megax.h b/simavr/cores/sim_megax.h
@@ -166,10 +166,20 @@ const struct mcu_t SIM_CORENAME = {
 	},
 	.timer0 = {
 		.name = '0',
+#ifdef OC0_PORT
+		.wgm = { AVR_IO_REGBIT(TCCR0, WGM00), AVR_IO_REGBIT(TCCR0, WGM01)},
+		.wgm_op = {
+			[0] = AVR_TIMER_WGM_NORMAL8(),
+			// TODO: 1 PWM phase correct 8bit
+			[2] = AVR_TIMER_WGM_CTC(),
+			[3] = AVR_TIMER_WGM_FASTPWM8(),
+		},
+#else
 		.wgm_op = {
 			[0] = AVR_TIMER_WGM_NORMAL8(),
 			// CTC etc. are missing because atmega8 does not support them on timer0
 		},
+#endif
 		.cs = { AVR_IO_REGBIT(TCCR0, CS00), AVR_IO_REGBIT(TCCR0, CS01), AVR_IO_REGBIT(TCCR0, CS02) },
 		.cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */, AVR_TIMER_EXTCLK_CHOOSE, AVR_TIMER_EXTCLK_CHOOSE  /* AVR_TIMER_EXTCLK_CHOOSE means External clock chosen*/},