initial risc-v core in Calyx

.gitignore

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+target/
+*.vcd
+*.ron

README.org

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+* Experimenting with writing a simple processor in Calyx
+
+* Some useful commands
+
+Encode =simple.s= into Calyx data format.
+
+#+begin_src async-shell :name encode :results none :dir ~/Research/calyx-processor/riscv-to-calyx
+cargo run -- encode data/simple.s \
+      --data ram:16:32:1 \
+      --data reg_file:32:32 \
+      --data dbg:1:32 \
+      -o ../data/simple.json
+#+end_src
+
+Decode a calyx data file and read assembly instructions.
+
+#+begin_src async-shell :name decode :results none :dir ~/Research/calyx-processor/riscv-to-calyx
+cargo run -- decode ../data/simple.json
+#+end_src
+
+Simulate the design with icarus verilog (was having some issues with Verilator)
+
+#+begin_src async-shell :name calyx-processor :results none
+cargo run --manifest-path=riscv-to-calyx/Cargo.toml -- \
+      encode riscv-to-calyx/data/simple.s \
+      --data ram:16:32:1 \
+      --data reg_file:32:32 \
+      --data dbg:1:32 \
+      -o data/simple.json
+
+fud e -q src/main.futil \
+    -s verilog.data data/simple.json \
+    --to dat --through icarus-verilog \
+    -s verilog.cycle_limit 100000 | cargo run --manifest-path=riscv-to-calyx/Cargo.toml -- decode
+#+end_src
+
+Debug the design with a lovely vcd file
+
+#+begin_src async-shell :name gen-vcd :results none
+fud e src/main.futil \
+    -s verilog.data data/simple.json \
+    --to vcd --through icarus-verilog \
+    -s calyx.flags " -p no-opt" \
+    -s verilog.cycle_limit 1000 \
+    -o dbg.vcd
+#+end_src

data/simple.json

@@ -0,0 +1,100 @@
+{
+  "reg_file": {
+    "data": [
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0,
+      0
+    ],
+    "format": {
+      "numeric_type": "bitnum",
+      "is_signed": false,
+      "width": 32
+    }
+  },
+  "insts": {
+    "data": [
+      1299,
+      10487187,
+      659,
+      787,
+      11755107,
+      2298771,
+      7668659,
+      238467,
+      7504563,
+      1245971,
+      4271894639,
+      165139,
+      32871
+    ],
+    "format": {
+      "numeric_type": "bitnum",
+      "is_signed": false,
+      "width": 32
+    }
+  },
+  "ram": {
+    "data": [
+      1,
+      1,
+      1,
+      1,
+      1,
+      1,
+      1,
+      1,
+      1,
+      1,
+      1,
+      1,
+      1,
+      1,
+      1,
+      1
+    ],
+    "format": {
+      "numeric_type": "bitnum",
+      "is_signed": false,
+      "width": 32
+    }
+  },
+  "dbg": {
+    "data": [
+      0
+    ],
+    "format": {
+      "numeric_type": "bitnum",
+      "is_signed": false,
+      "width": 32
+    }
+  }
+}