GitHub - chanceraine/VerilogProject: A tomasulo based processor with prefetching

Name		Name	Last commit message	Last commit date
Latest commit History 11 Commits
Makefile		Makefile
PROPOSAL.txt		PROPOSAL.txt
README		README
REPORT.txt		REPORT.txt
add.v		add.v
bPredictor.v		bPredictor.v
cache.v		cache.v
clock.v		clock.v
counter.v		counter.v
cpu		cpu
cpu.v		cpu.v
cpu.vcd		cpu.vcd
isb.v		isb.v
load.v		load.v
mem.hex		mem.hex
mem.v		mem.v
mem1.hex		mem1.hex
mem2.hex		mem2.hex
mem3.hex		mem3.hex
mem4.hex		mem4.hex
mem5.hex		mem5.hex
mem6.hex		mem6.hex
mem7.hex		mem7.hex
mem8.hex		mem8.hex
mem9.hex		mem9.hex
mema.hex		mema.hex
memb.hex		memb.hex
memc.hex		memc.hex
memd.hex		memd.hex
meme.hex		meme.hex
memf.hex		memf.hex
memg.hex		memg.hex
memh.hex		memh.hex
memi.hex		memi.hex
memj.hex		memj.hex
memk.hex		memk.hex
memm.hex		memm.hex
memn.hex		memn.hex
memn.ok		memn.ok
memw.hex		memw.hex
memz.hex		memz.hex
prefetcher.v		prefetcher.v
test.cycles		test.cycles
test.ok		test.ok
test.out		test.out
test.raw		test.raw
test1.ok		test1.ok
test2.ok		test2.ok
test3.ok		test3.ok
test4.ok		test4.ok
test5.ok		test5.ok
test6.ok		test6.ok
test7.ok		test7.ok
test8.ok		test8.ok
test9.ok		test9.ok
testa.ok		testa.ok
testb.ok		testb.ok
testc.ok		testc.ok
testd.ok		testd.ok
teste.ok		teste.ok
testf.ok		testf.ok
testg.ok		testg.ok
testh.ok		testh.ok
testi.ok		testi.ok
testj.ok		testj.ok
testk.ok		testk.ok
testm.ok		testm.ok
testw.ok		testw.ok
testz.ok		testz.ok

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Due dates:

PROPOSAL.txt : 4/26/2015 @ 11:59pm
REPORT.txt & working code & tests : 5/8/2015 @ 11:59pm