🎯
Focusing
Postdoc at EPFL, studying logic synthesis and verification for emerging technologies.
-
École Polytechnique Fédérale de Lausanne
- Laussane, Switzerland
-
09:32
(UTC +02:00) - https://changmg.github.io/
Highlights
- Pro
Pinned Loading
-
SJTU-ECTL/ALSRAC
SJTU-ECTL/ALSRAC PublicALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
-
SJTU-ECTL/VECBEE
SJTU-ECTL/VECBEE PublicVECBEE: A Versatile Efficiency-Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis
-
SJTU-ECTL/HEDALS
SJTU-ECTL/HEDALS PublicHighly efficient delay-driven approximate logic synthesis
-
SJTU-ECTL/MECALS
SJTU-ECTL/MECALS PublicAn approximate logic synthesis tool under the maximum error constraint
Verilog 4
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.