deploy: 892ff73

preview/155/index.xml

@@ -95,6 +95,6 @@ THe CHIPS Alliance is hosted by The Linux Foundation, a 501(c)6 non-profit.</des
 Rob Mains - General Manager The General Manager works with the Governing Board, our members, and our projects to ensure the CHIPS Alliance is a healthy, sustainable, and neutral home for open source technical collaborations.</description></item><item><title>Interconnect Workgroup</title><link>https://chipsalliance.org/preview/155/workgroups/interconnect/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/preview/155/workgroups/interconnect/</guid><description>The Interconnect workgroup researches open networking protocols to facilitate direct coherency messaging between components such as processor caches, memory controllers, and various accelerators in RISC-V cores. The interconnections provided by this group play a crucial role in SoCs, chiplets, and various hardware designs. We offer design guidelines for interconnects and manage open-source interconnect IP based on these guidelines. Interconnect WG supports the advancement of the open-source hardware ecosystem.</description></item><item><title>Join</title><link>https://chipsalliance.org/preview/155/join/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/preview/155/join/</guid><description>The CHIPS Alliance is an organization which works collaboratively to develop high quality, open source hardware designs relevant to silicon devices and FPGAs. By sharing openly resources and ideas, we hope to lower the cost of hardware development.
 As a collection of open source projects, anyone is welcome to participate in the technical development process. The Technical Advisory Council oversees the technical direction of the project.
 The CHIPS Alliance also welcomes corporate members.</description></item><item><title>Members</title><link>https://chipsalliance.org/preview/155/about/members/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/preview/155/about/members/</guid><description>When an organization joins the CHIPS Alliance, they are making a tangible commitment to the success and sustainability of open source projects which help to achieve these goals. The CHIPS Alliance recognizes the critical supporting role of these organizations, and thanks them for their ongoing support of our project communities.
-CHIPS Alliance Members Become a Member Platinum Members Gold Members Silver Members Auditor Members Associate Members</description></item><item><title>Projects</title><link>https://chipsalliance.org/preview/155/projects/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/preview/155/projects/</guid><description>Graduated Projects Caliptra The Caliptra project focuses on development of HW and SW IP for the Caliptra Root of Trust Repositories: caliptra caliptra-rtl caliptra-sw caliptra-ureg caliptra-dpe Issue Tracker Website Contact: Andres Lagar-Cavilla (GitHub) F4PGA Free and open source toolchain for FPGA devices Repositories: f4pga Issue Tracker Website Contact: Tomasz Michalak (GitHub) FPGA Interchange format FPGA Interchange is a Vendor agnostic FPGA devices and designs description.</description></item><item><title>Rocket Workgroup</title><link>https://chipsalliance.org/preview/155/workgroups/rocket/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/preview/155/workgroups/rocket/</guid><description>The Rocket Chip Workgroup covers the “Rocket” pipelined implementation of a RISC-V core as well as a TileLink uncore and cache coherent memory hierarchy. The main rocket-chip repository that the group maintains is a meta-repository containing tools needed to generate and test RTL implementations of SoC designs. This repository contains code that is used to generate RTL using Chisel and Diplomacy: the Rocket Chip generator itself is a Scala program that invokes the Diplomacy library and Chisel compiler in order to emit RTL describing a complete SoC.</description></item><item><title>Tools Workgroup</title><link>https://chipsalliance.org/preview/155/workgroups/tools/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/preview/155/workgroups/tools/</guid><description>The Tools workgroup (WG) of CHIPS Alliance covers a wide array of open source tooling for ASIC and FPGA design, mostly focusing around digital design (as there is a separate Analog WG that focuses on AMS design flows). The topics covered include simulation, synthesis, place and route, IP aggregation, linting, formatting, and many more.</description></item><item><title>Who We Are</title><link>https://chipsalliance.org/preview/155/about/who-we-are/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/preview/155/about/who-we-are/</guid><description>The CHIPS Alliance leverages common hardware development efforts by developing IP blocks that can be broadly used, such as RISC-V cores and neural network accelerator cores. We recognize that verification contributions benefit all who participate in the project, and prioritize joint resources for design verification.
+CHIPS Alliance Members Become a Member Platinum Members Gold Members Silver Members Auditor Members Associate Members</description></item><item><title>Projects</title><link>https://chipsalliance.org/preview/155/projects/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/preview/155/projects/</guid><description>Graduated Projects Caliptra The Caliptra project focuses on development of HW and SW IP for the Caliptra Root of Trust Repositories: caliptra caliptra-rtl caliptra-sw caliptra-ureg caliptra-dpe Issue Tracker Website Contact: Andres Lagar-Cavilla (GitHub) FPGA Interchange format FPGA Interchange is a Vendor agnostic FPGA devices and designs description. It enables interoperability between different FPGA tools.</description></item><item><title>Rocket Workgroup</title><link>https://chipsalliance.org/preview/155/workgroups/rocket/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/preview/155/workgroups/rocket/</guid><description>The Rocket Chip Workgroup covers the “Rocket” pipelined implementation of a RISC-V core as well as a TileLink uncore and cache coherent memory hierarchy. The main rocket-chip repository that the group maintains is a meta-repository containing tools needed to generate and test RTL implementations of SoC designs. This repository contains code that is used to generate RTL using Chisel and Diplomacy: the Rocket Chip generator itself is a Scala program that invokes the Diplomacy library and Chisel compiler in order to emit RTL describing a complete SoC.</description></item><item><title>Tools Workgroup</title><link>https://chipsalliance.org/preview/155/workgroups/tools/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/preview/155/workgroups/tools/</guid><description>The Tools workgroup (WG) of CHIPS Alliance covers a wide array of open source tooling for ASIC and FPGA design, mostly focusing around digital design (as there is a separate Analog WG that focuses on AMS design flows). The topics covered include simulation, synthesis, place and route, IP aggregation, linting, formatting, and many more.</description></item><item><title>Who We Are</title><link>https://chipsalliance.org/preview/155/about/who-we-are/</link><pubDate>Mon, 01 Jan 0001 00:00:00 +0000</pubDate><guid>https://chipsalliance.org/preview/155/about/who-we-are/</guid><description>The CHIPS Alliance leverages common hardware development efforts by developing IP blocks that can be broadly used, such as RISC-V cores and neural network accelerator cores. We recognize that verification contributions benefit all who participate in the project, and prioritize joint resources for design verification.
 The scope of the Project includes hardware and software design and development under an open source (Apache v2) license:
 Verified IP blocks (compute cores, accelerators etc) Verified SoC designs (based on RISC-V and other open source cores) Open source software development tools for ASIC development High value IP including analog peripherals, mixed signal blocks and compute acceleration Exploration of new design flows such as Python-based design verification.</description></item></channel></rss>

preview/155/news/caliptra-support-for-veer/index.html

@@ -126,7 +126,6 @@ <h1>Caliptra - Support for VeeR EL2 with User Mode and Physical Memory Protectio
 </div>
 <div><p>The <a href=https://chipsalliance.github.io/Caliptra/>Caliptra</a> Root of Trust project, a collaboration between AMD, Google, Microsoft and NVIDIA within the <a href=https://www.chipsalliance.org/>CHIPS Alliance</a>, is steadily heading towards its <a href=https://www.chipsalliance.org/news/caliptra-ocp-global-summit-2024/>2.0 release</a> – an effort Antmicro is <a href="https://www.youtube.com/watch?v=hXjUoCGlXyM">actively contributing to</a>. They’ve recently described their <a href=https://antmicro.com/blog/2024/09/user-mode-in-veer-el2-core-for-caliptra-2-0/>implementation of User mode</a> in the RISC-V VeeR EL2 core along with extended Physical Memory Protection, and related to this work, they’ve introduced support for VeeR EL2 with User Mode and PMP to the <a href=https://github.com/tock/tock>Tock</a> embedded OS. The main goal of this implementation was to test the mode switching feature of the VeeR EL2 core with PMP enabled.</p>
 <p>In this article we’ll describe implementation details, including Antmicro’s contributions to Tock, <a href=https://github.com/tock/libtock-c>libtock-c</a> and <a href=https://github.com/tock/tockloader>tockloader</a>. We’ll also show an <a href=https://github.com/chipsalliance/VeeR-EL2-tock-example>example</a> in which a Tock application running on a VeeR EL2 core simulated in <a href=https://www.veripool.org/verilator/>Verilator</a> performs forbidden memory accesses, demonstrating that PMP enforces proper User mode constraints.</p>
-<p><img src=VeeR-EL2-Tock--blog-sm.png alt="Support for VeeR EL2 in Tock OS illustration"></p>
 <h3 id=adding-new-platforms-to-tock-os>Adding new platforms to Tock OS</h3>
 <p><a href=https://tockos.org/>Tock</a> is an embedded operating system written in Rust, designed for running multiple concurrent, mutually distrustful applications on Cortex-M and RISC-V based platforms. As it provides isolation between components to ensure safety and security, it’s a popular choice for Root of Trust projects, such as <a href=https://antmicro.com/blog/2023/03/adapting-opentitan-for-fpga-prototyping-and-tooling-development/>OpenTitan</a> used e.g. in Google’s <a href=https://antmicro.com/blog/2023/11/secure-open-source-ml-with-open-se-cura/>Open Se Cura</a> project that Antmicro has also been involved with.</p>
 <p>When adding support for a new platform in Tock, we need to consider <a href=https://book.tockos.org/development/porting.html#crate-details>three layers of support</a>: architecture, chip and board. Tock already supports several RISC-V platforms as well as the RISC-V privilege spec with Machine, Supervisor and User modes. When introducing support for VeeR in Tock, we were able to reuse the implementation of RISC-V-specific components, i.e. the general architecture support, machine timer and interrupt controller.</p>

preview/155/projects/index.html

@@ -155,26 +155,6 @@ <h3 class=mt-0>Caliptra</h3>
 </div>
 <div class="projects-box mb-5">
 <div class=projects-box-col1>
-<a href=https://f4pga.org target=_blank>
-<img src=/preview/155/images/projects/f4pga.svg loading=lazy alt=F4PGA>
-</a>
-</div>
-<div class=projects-box-col2>
-<h3 class=mt-0>F4PGA</h3>
-<p> Free and open source toolchain for FPGA devices </p>
-<ul class=list-unstyled>
-<li>Repositories:</li>
-<ul class="list-unstyled mb-0 ms-5">
-<li><i class=ph-git-branch></i> <a href=https://github.com/chipsalliance/f4pga target=_blank>f4pga</a></li>
-</ul>
-<li><i class=ph-clipboard-text></i> <a href=https://github.com/chipsalliance/f4pga/issues target=_blank>Issue Tracker</a></li>
-<i class=ph-link></i> <a href=https://f4pga.org target=_blank>Website</a>
-<li><i class=ph-user-square></i> <a href=mailto:tmichalak@antmicro.com target=_blank>Contact: Tomasz Michalak</a> (<a href=https://github.com/tmichalak target=_blank>GitHub</a>)</li>
-</ul>
-</div>
-</div>
-<div class="projects-box mb-5">
-<div class=projects-box-col1>
 <a href=https://fpga-interchange-schema.readthedocs.io/ target=_blank>
 <img src=/preview/155/images/muted-logo.svg loading=lazy alt="Placeholder project logo">
 </a>
@@ -216,6 +196,26 @@ <h3 class=mt-0>FPGA tool perf</h3>
 </div>
 <div class="projects-box mb-5">
 <div class=projects-box-col1>
+<a href=https://f4pga.org target=_blank>
+<img src=/preview/155/images/projects/f4pga.svg loading=lazy alt=F4PGA>
+</a>
+</div>
+<div class=projects-box-col2>
+<h3 class=mt-0>F4PGA</h3>
+<p> Free and open source toolchain for FPGA devices </p>
+<ul class=list-unstyled>
+<li>Repositories:</li>
+<ul class="list-unstyled mb-0 ms-5">
+<li><i class=ph-git-branch></i> <a href=https://github.com/chipsalliance/f4pga target=_blank>f4pga</a></li>
+</ul>
+<li><i class=ph-clipboard-text></i> <a href=https://github.com/chipsalliance/f4pga/issues target=_blank>Issue Tracker</a></li>
+<i class=ph-link></i> <a href=https://f4pga.org target=_blank>Website</a>
+<li><i class=ph-user-square></i> <a href=mailto:tmichalak@antmicro.com target=_blank>Contact: Tomasz Michalak</a> (<a href=https://github.com/tmichalak target=_blank>GitHub</a>)</li>
+</ul>
+</div>
+</div>
+<div class="projects-box mb-5">
+<div class=projects-box-col1>
 <a href=https://github.com/chipsalliance/systemc-compiler/wiki target=_blank>
 <img src=/preview/155/images/muted-logo.svg loading=lazy alt="Placeholder project logo">
 </a>
@@ -411,41 +411,41 @@ <h2 class=mt-3>Sandbox Projects</h2>
 <div class=blog-post-content>
 <div class="projects-box mb-5">
 <div class=projects-box-col1>
-<a href=https://github.com/brightai-nl/BlackwireOverview/ target=_blank>
-<img src=/preview/155/images/muted-logo.svg loading=lazy alt="Placeholder project logo">
+<a href=https://www.chisel-lang.org/ target=_blank>
+<img src=/preview/155/images/projects/chisel.svg loading=lazy alt=Chisel>
 </a>
 </div>
 <div class=projects-box-col2>
-<h3 class=mt-0>Blackwire</h3>
-<p> Full inline accelerator of WireGuard </p>
+<h3 class=mt-0>Chisel</h3>
+<p> Support the Chisel Hardware Construction Language and related projects </p>
 <ul class=list-unstyled>
 <li>Repositories:</li>
 <ul class="list-unstyled mb-0 ms-5">
-<li><i class=ph-git-branch></i> <a href=https://github.com/orgs/brightai-nl/repositories target=_blank>repositories</a></li>
+<li><i class=ph-git-branch></i> <a href=https://github.com/chipsalliance/chisel target=_blank>chisel</a></li>
 </ul>
-<li><i class=ph-clipboard-text></i> <a href=https://github.com/brightai-nl/BlackwireOverview/issues target=_blank>Issue Tracker</a></li>
-<i class=ph-link></i> <a href=https://github.com/brightai-nl/BlackwireOverview/ target=_blank>Website</a>
-<li><i class=ph-user-square></i> <a href=mailto:b.c.knijff@fpgahouse.com target=_blank>Contact: Ben Knijff</a> (<a href=https://github.com/brightai-nl target=_blank>GitHub</a>)</li>
+<li><i class=ph-clipboard-text></i> <a href=https://github.com/chipsalliance/chisel/issues target=_blank>Issue Tracker</a></li>
+<i class=ph-link></i> <a href=https://www.chisel-lang.org/ target=_blank>Website</a>
+<li><i class=ph-user-square></i> <a href=mailto:koenig@sifive.com target=_blank>Contact: Jack Koenig</a> (<a href=https://github.com/https://github.com/jackkoenig target=_blank>GitHub</a>)</li>
 </ul>
 </div>
 </div>
 <div class="projects-box mb-5">
 <div class=projects-box-col1>
-<a href=https://www.chisel-lang.org/ target=_blank>
-<img src=/preview/155/images/projects/chisel.svg loading=lazy alt=Chisel>
+<a href=https://github.com/brightai-nl/BlackwireOverview/ target=_blank>
+<img src=/preview/155/images/muted-logo.svg loading=lazy alt="Placeholder project logo">
 </a>
 </div>
 <div class=projects-box-col2>
-<h3 class=mt-0>Chisel</h3>
-<p> Support the Chisel Hardware Construction Language and related projects </p>
+<h3 class=mt-0>Blackwire</h3>
+<p> Full inline accelerator of WireGuard </p>
 <ul class=list-unstyled>
 <li>Repositories:</li>
 <ul class="list-unstyled mb-0 ms-5">
-<li><i class=ph-git-branch></i> <a href=https://github.com/chipsalliance/chisel target=_blank>chisel</a></li>
+<li><i class=ph-git-branch></i> <a href=https://github.com/orgs/brightai-nl/repositories target=_blank>repositories</a></li>
 </ul>
-<li><i class=ph-clipboard-text></i> <a href=https://github.com/chipsalliance/chisel/issues target=_blank>Issue Tracker</a></li>
-<i class=ph-link></i> <a href=https://www.chisel-lang.org/ target=_blank>Website</a>
-<li><i class=ph-user-square></i> <a href=mailto:koenig@sifive.com target=_blank>Contact: Jack Koenig</a> (<a href=https://github.com/https://github.com/jackkoenig target=_blank>GitHub</a>)</li>
+<li><i class=ph-clipboard-text></i> <a href=https://github.com/brightai-nl/BlackwireOverview/issues target=_blank>Issue Tracker</a></li>
+<i class=ph-link></i> <a href=https://github.com/brightai-nl/BlackwireOverview/ target=_blank>Website</a>
+<li><i class=ph-user-square></i> <a href=mailto:b.c.knijff@fpgahouse.com target=_blank>Contact: Ben Knijff</a> (<a href=https://github.com/brightai-nl target=_blank>GitHub</a>)</li>
 </ul>
 </div>
 </div>