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Merge pull request #530 from antmicro/umarcor/add-pyFPGA
Add sfbuild|pyF4PGA
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,43 @@ | ||
| { | ||
| "default_platform": "xc7a50t", | ||
| "values": { | ||
| "top": "top" | ||
| }, | ||
| "dependencies": { | ||
| "sources": [ | ||
| "xc7/counter_test/counter.v" | ||
| ], | ||
| "synth_log": "synth.log", | ||
| "pack_log": "pack.log" | ||
| }, | ||
| "xc7a200t": { | ||
| "default_target": "bitstream", | ||
| "dependencies": { | ||
| "xdc": [ | ||
| "arty200.xdc" | ||
| ], | ||
| "build_dir": "build/arty_200" | ||
| } | ||
| }, | ||
| "xc7a100t": { | ||
| "default_target": "bitstream", | ||
| "dependencies": { | ||
| "xdc": [ | ||
| "arty.xdc" | ||
| ], | ||
| "build_dir": "build/arty100" | ||
| } | ||
| }, | ||
| "xc7a50t": { | ||
| "default_target": "bitstream", | ||
| "dependencies": { | ||
| "build_dir": "build/arty_35", | ||
| "xdc": [ | ||
| "arty.xdc" | ||
| ] | ||
| }, | ||
| "values": { | ||
| "part": "xc7a35tcpg236-1" | ||
| } | ||
| } | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,2 +1,3 @@ | ||
| *.pyc | ||
| *.sw* | ||
| /f4pga/build/ |
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| Original file line number | Diff line number | Diff line change |
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| # Developer's notes | ||
| ##### Last update: 2022-05-06 | ||
|
|
||
| :::{warning} | ||
| These notes are provided as-is and they shouldn't be treated as a full-blown accurate | ||
| documentation, but rather as a helpful resource for those who want to get involved with | ||
| development of _f4pga_. These are not updated regularly. | ||
|
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| For more detailed, up-to-date information about the code, refer to the pydoc documentation. | ||
| ::: | ||
|
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| ## Project's structure | ||
|
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| * `__init__.py` contains the logic and entry point of the build system | ||
| * `argparser.py` contains boring code for CLI interface | ||
| * `cache.py` contains code needed for tracking modifications in the project. | ||
| * `common.py` contains code shared by the main utility and the modules | ||
| * `flow_config.py` contains code for reading and accessing flow definitions and configurations | ||
| * `module_inspector.py` contains utilities for inspecting I/O of modules | ||
| * `module_runner.py` contains code required to load modules at run-time | ||
| * `module.py` contains definitions required for writing and using f4pga modules | ||
| * `part_db.json` contains mappings from part names to platform names | ||
| * `setup.py` contains a package installation script | ||
| * `stage.py` contains classes relevant to stage representation | ||
| * `modules` contains loadable modules | ||
| * `platforms` contains platform flow definitions | ||
|
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||
| :::{important} | ||
| Through the codebase _f4pga_ (tool) might be often referenced as _sfbuild_. | ||
| Similarly, _F4PGA_ (toolchain) might get called _Symbiflow_. | ||
| This is due to the project being written back when _F4PGA_ was called _Symbiflow_. | ||
| ::: | ||
|
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| ## Different subsystems and where to find them? | ||
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| ### Building and dependency resolution | ||
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| All the code regarding dependency resolution is located in `__init__.py` file. | ||
| Take a look at the `Flow` class. | ||
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| Most of the work is done in `Flow._resolve_dependencies` method. Basically it | ||
| performs a _DFS_ with _stages_ (instances of _f4pga modules_) as its nodes | ||
| which are linked using symbolic names of dependencies on inputs and outputs. | ||
| It queries the modules for information regarding i/o (most importantly the paths | ||
| on which they are going to produce outputs), checks whether | ||
| their inputs are going to be satisfied, checks if dependencies were modified, etc. | ||
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| The actual building is done using `Flow._build_dep` procedure. It uses a similar | ||
| _DFS_ approach to invoke modules and check their inputs and outputs. | ||
|
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| ### Modification tracking | ||
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| Modification tracking is done by taking, comparing and keeping track of `adler32` | ||
| hashes of all dependencies. Each dependency has a set of hashes associated with it. | ||
| The reason for having multiple hashes is that a dependency may have multiple | ||
| "_consumers_", ie. _stages_ which take it as input. Each hash is associated with | ||
| particular consumer. This is necessary, because the system tries to avoid rebuilds | ||
| when possible and status of each file (modified/unmodified) may differ in regards | ||
| to individual stages. | ||
|
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| Keeping track of status of each file is done using `SymbiCache` class, which is | ||
| defined in `sf_cache.py` file. `SymbiCache` is used mostly inside `Flow`'s methods. | ||
|
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| ### Internal environmental variable system | ||
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| _f4pga_ exposes some data to the user as well as reads some using internal | ||
| environmental variables. These can be referenced by users in | ||
| _platform flow definitions_ and _project flow configurations_ using the | ||
| `${variable_name}` syntax when defining values. They can also be read inside | ||
| _f4pga modules_ by accessing the `ctx.values` namespace. | ||
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| The core of its system is the `ResolutionEnvironemt` class which can be found | ||
| inside the `common` module. | ||
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| ### Installation | ||
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| Check `CMakeLists.txt`. | ||
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| ## TODO: | ||
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| * Define a clear specification for entries in _platform flow definitions_ and | ||
| _platform flow configurations_. Which environmental variables can be accessed | ||
| where, and when? | ||
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| * Force "_on-demand_" outputs if they are required by another stage. | ||
| This may require redesigning the "on-demand" feature, which currently works | ||
| by producing a dependency if and only if the user explicitly provides the | ||
| path. Otherwise the path is unknown. | ||
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| * Make commenting style consistent | ||
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| * Document writing flow definitions | ||
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| * Extend the metadata system for modules, perhaps make it easier to use. | ||
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| * Add missing metadata for module targets. | ||
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| * (_suggestion_) Generate platform definitions using CMake. | ||
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| ### Out of the current scope | ||
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| * Change interfaces of some internal python scripts. This could lead to possibly | ||
| merging some modules for XC7 and Quicklogic into one common module. |
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