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Bump to latest spike #29

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merged 1 commit into from
Feb 14, 2024
Merged

Bump to latest spike #29

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2 changes: 1 addition & 1 deletion .github/workflows/build-and-test.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ jobs:
run: |
git clone https://github.com/riscv-software-src/riscv-isa-sim.git
cd riscv-isa-sim
git reset --hard 5a1145742e701597eb45825855311dfad21232a6
git reset --hard 3a53c80ade3336b1d46c9db3a6c6be8311c32cc5
mkdir build
cd build
../configure --prefix=${{ github.workspace }}/riscv
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18 changes: 3 additions & 15 deletions pspike/pspike.cc
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Expand Up @@ -58,19 +58,7 @@ class magic_extension_t : public extension_t {
int main(int argc, char** argv) {
std::vector<mem_cfg_t> mem_cfg { mem_cfg_t(0x80000000, 0x10000000) };
std::vector<size_t> hartids = {0};
cfg_t cfg(std::make_pair(0, 0),
nullptr,
"rv64gcv",
"MSU",
"vlen:128,elen:64",
false,
endianness_little,
16,
mem_cfg,
hartids,
false,
4);

cfg_t cfg;
option_parser_t parser;
parser.option(0, "isa", 1, [&](const char* s){cfg.isa = s;});
parser.option(0, "varch", 1, [&](const char* s){cfg.varch = s;});
Expand All @@ -89,8 +77,8 @@ int main(int argc, char** argv) {
.support_haltgroups = true,
.support_impebreak = true
};
std::vector<std::pair<reg_t, abstract_mem_t*>> mems = make_mems(cfg.mem_layout());
std::vector<const device_factory_t*> plugin_devices;
std::vector<std::pair<reg_t, abstract_mem_t*>> mems = make_mems(cfg.mem_layout);
std::vector<device_factory_t*> plugin_devices;
sim_t sim(&cfg, false,
mems,
plugin_devices,
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