[build system] fix elaborators of modules containing SRAMDescription

chipsalliance · Oct 21, 2024 · 20b0367 · 20b0367
1 parent 14308a3
commit 20b0367
Show file tree

Hide file tree

Showing 7 changed files with 21 additions and 0 deletions.
diff --git a/elaborator/src/rocketv/Frontend.scala b/elaborator/src/rocketv/Frontend.scala
@@ -5,6 +5,7 @@ package org.chipsalliance.t1.elaborator.rocketv
 import chisel3.experimental.util.SerializableModuleElaborator
 import chisel3.util.BitPat
 import chisel3.util.experimental.BitSet
+import chisel3.stage.IncludeUtilMetadata
 import mainargs._
 import org.chipsalliance.rocketv.{BHTParameter, Frontend, FrontendParameter}
 
@@ -136,6 +137,8 @@ object Frontend extends SerializableModuleElaborator {
   implicit def FrontendParameterMainParser: ParserForClass[FrontendParameterMain] =
     ParserForClass[FrontendParameterMain]
 
+  override def additionalAnnotations = Seq(IncludeUtilMetadata)
+
   @main
   def config(@arg(name = "parameter") parameter: M) =
     os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert))

diff --git a/elaborator/src/rocketv/ICache.scala b/elaborator/src/rocketv/ICache.scala
@@ -3,6 +3,7 @@
 package org.chipsalliance.t1.elaborator.rocketv
 
 import chisel3.experimental.util.SerializableModuleElaborator
+import chisel3.stage.IncludeUtilMetadata
 import mainargs._
 import org.chipsalliance.rocketv.{ICache, ICacheParameter}
 
@@ -41,6 +42,8 @@ object ICache extends SerializableModuleElaborator {
 
   implicit def ICacheParameterMainParser: ParserForClass[ICacheParameterMain] = ParserForClass[ICacheParameterMain]
 
+  override def additionalAnnotations = Seq(IncludeUtilMetadata)
+
   @main
   def config(@arg(name = "parameter") parameter: M) =
     os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert))

diff --git a/elaborator/src/rocketv/RocketTile.scala b/elaborator/src/rocketv/RocketTile.scala
@@ -5,6 +5,7 @@ package org.chipsalliance.t1.elaborator.rocketv
 import chisel3.experimental.util.SerializableModuleElaborator
 import chisel3.util.BitPat
 import chisel3.util.experimental.BitSet
+import chisel3.stage.IncludeUtilMetadata
 import mainargs._
 import org.chipsalliance.rocketv.{BHTParameter, RocketTile, RocketTileParameter}
 
@@ -190,6 +191,8 @@ object RocketTile extends SerializableModuleElaborator {
   implicit def RocketTileParameterMainParser: ParserForClass[RocketTileParameterMain] =
     ParserForClass[RocketTileParameterMain]
 
+  override def additionalAnnotations = Seq(IncludeUtilMetadata)
+
   @main
   def config(@arg(name = "parameter") parameter: M) =
     os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert))

diff --git a/elaborator/src/t1/T1.scala b/elaborator/src/t1/T1.scala
@@ -3,6 +3,7 @@
 package org.chipsalliance.t1.elaborator.t1
 
 import chisel3.experimental.util.SerializableModuleElaborator
+import chisel3.stage.IncludeUtilMetadata
 import mainargs._
 import org.chipsalliance.t1.rtl.vrf.RamType
 import org.chipsalliance.t1.rtl.vrf.RamType.{p0rp1w, p0rw, p0rwp1rw}
@@ -58,6 +59,8 @@ object T1 extends SerializableModuleElaborator {
 
   implicit def T1ParameterMainParser: ParserForClass[M] = ParserForClass[M]
 
+  override def additionalAnnotations = Seq(IncludeUtilMetadata)
+
   @main
   def config(@arg(name = "parameter") parameter: M) =
     os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert))

diff --git a/elaborator/src/t1emu/TestBench.scala b/elaborator/src/t1emu/TestBench.scala
@@ -3,6 +3,7 @@
 package org.chipsalliance.t1.elaborator.t1emu
 
 import chisel3.experimental.util.SerializableModuleElaborator
+import chisel3.stage.IncludeUtilMetadata
 import mainargs._
 import org.chipsalliance.t1.rtl.vrf.RamType
 import org.chipsalliance.t1.rtl.vrf.RamType.{p0rp1w, p0rw, p0rwp1rw}
@@ -59,6 +60,8 @@ object TestBench extends SerializableModuleElaborator {
 
   implicit def T1ParameterMainParser: ParserForClass[M] = ParserForClass[M]
 
+  override def additionalAnnotations = Seq(IncludeUtilMetadata)
+
   @main
   def config(@arg(name = "parameter") parameter: M) =
     os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert))

diff --git a/elaborator/src/t1rocket/T1RocketTile.scala b/elaborator/src/t1rocket/T1RocketTile.scala
@@ -5,6 +5,7 @@ package org.chipsalliance.t1.elaborator.t1rocketv
 import chisel3.experimental.util.SerializableModuleElaborator
 import chisel3.util.BitPat
 import chisel3.util.experimental.BitSet
+import chisel3.stage.IncludeUtilMetadata
 import mainargs._
 import org.chipsalliance.t1.rtl.VFUInstantiateParameter
 import org.chipsalliance.t1.rtl.vrf.RamType
@@ -111,6 +112,8 @@ object T1RocketTile extends SerializableModuleElaborator {
   implicit def T1RocketTileParameterMainParser: ParserForClass[T1RocketTileParameterMain] =
     ParserForClass[T1RocketTileParameterMain]
 
+  override def additionalAnnotations = Seq(IncludeUtilMetadata)
+
   @main
   def config(@arg(name = "parameter") parameter: M) =
     os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert))

diff --git a/elaborator/src/t1rocketemu/TestBench.scala b/elaborator/src/t1rocketemu/TestBench.scala
@@ -5,6 +5,7 @@ package org.chipsalliance.t1.elaborator.t1rocketemu
 import chisel3.experimental.util.SerializableModuleElaborator
 import chisel3.util.BitPat
 import chisel3.util.experimental.BitSet
+import chisel3.stage.IncludeUtilMetadata
 import mainargs._
 import org.chipsalliance.t1.rtl.VFUInstantiateParameter
 import org.chipsalliance.t1.rtl.vrf.RamType
@@ -112,6 +113,8 @@ object TestBench extends SerializableModuleElaborator {
   implicit def T1RocketTileParameterMainParser: ParserForClass[T1RocketTileParameterMain] =
     ParserForClass[T1RocketTileParameterMain]
 
+  override def additionalAnnotations = Seq(IncludeUtilMetadata)
+
   @main
   def config(@arg(name = "parameter") parameter: M) =
     os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert))