[ipemu] Add XiZhiMen for capture all probe signals for debuging.

ipemu/src/TestBench.scala

@@ -6,6 +6,7 @@ package org.chipsalliance.t1.ipemu
 import chisel3._
 import chisel3.experimental.SerializableModuleGenerator
 import chisel3.probe._
+import chisel3.util.experimental.BoringUtils.bore
 import org.chipsalliance.t1.ipemu.dpi._
 import org.chipsalliance.t1.rtl.{T1, T1Parameter}
 
@@ -48,6 +49,22 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter]) extends
 
   val t1Probe = probe.read(dut.t1Probe).suggestName("instructionCountProbe")
 
+  // Monitor
+  Module(new Module {
+    // h/t: GrandCentral
+    override def desiredName: String = "XiZhiMen"
+    // Gather all probe signals from dut.
+    // this is a hack when we don't have any performance pointer.
+    chisel3.reflect.DataMirror.modulePorts(dut).foreach{ case (name, data) =>
+      if(chisel3.reflect.DataMirror.hasProbeTypeModifier(data)) {
+        // to avoid create IO and on the Monitor Module, we just bore it.
+        // Notice: only verification API don't need a stable IO.
+        val monitor: Data = bore(data).suggestName(name)
+        dontTouch(monitor)
+      }
+    }
+  })
+
   // Monitors
   // TODO: These monitors should be purged out after offline difftest is landed
   val peekLsuEnq = Module(new PeekLsuEnq(PeekLsuEnqParameter(dut.parameter.lsuParameters.lsuMSHRSize, latPeekLsuEnq)))