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Fix elaborators of modules containing SRAMDescription #814

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merged 2 commits into from
Oct 21, 2024
Merged

Fix elaborators of modules containing SRAMDescription #814

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2555596
[deps] Bump T1 dependencies
Avimitin Oct 20, 2024
a08ba7d
[build system] fix elaborators of modules containing SRAMDescription
unlsycn Oct 21, 2024
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3 changes: 3 additions & 0 deletions elaborator/src/rocketv/Frontend.scala
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Expand Up @@ -5,6 +5,7 @@ package org.chipsalliance.t1.elaborator.rocketv
import chisel3.experimental.util.SerializableModuleElaborator
import chisel3.util.BitPat
import chisel3.util.experimental.BitSet
import chisel3.stage.IncludeUtilMetadata
import mainargs._
import org.chipsalliance.rocketv.{BHTParameter, Frontend, FrontendParameter}

Expand Down Expand Up @@ -136,6 +137,8 @@ object Frontend extends SerializableModuleElaborator {
implicit def FrontendParameterMainParser: ParserForClass[FrontendParameterMain] =
ParserForClass[FrontendParameterMain]

override def additionalAnnotations = Seq(IncludeUtilMetadata)

@main
def config(@arg(name = "parameter") parameter: M) =
os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert))
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3 changes: 3 additions & 0 deletions elaborator/src/rocketv/ICache.scala
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Expand Up @@ -3,6 +3,7 @@
package org.chipsalliance.t1.elaborator.rocketv

import chisel3.experimental.util.SerializableModuleElaborator
import chisel3.stage.IncludeUtilMetadata
import mainargs._
import org.chipsalliance.rocketv.{ICache, ICacheParameter}

Expand Down Expand Up @@ -41,6 +42,8 @@ object ICache extends SerializableModuleElaborator {

implicit def ICacheParameterMainParser: ParserForClass[ICacheParameterMain] = ParserForClass[ICacheParameterMain]

override def additionalAnnotations = Seq(IncludeUtilMetadata)

@main
def config(@arg(name = "parameter") parameter: M) =
os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert))
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3 changes: 3 additions & 0 deletions elaborator/src/rocketv/RocketTile.scala
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Expand Up @@ -5,6 +5,7 @@ package org.chipsalliance.t1.elaborator.rocketv
import chisel3.experimental.util.SerializableModuleElaborator
import chisel3.util.BitPat
import chisel3.util.experimental.BitSet
import chisel3.stage.IncludeUtilMetadata
import mainargs._
import org.chipsalliance.rocketv.{BHTParameter, RocketTile, RocketTileParameter}

Expand Down Expand Up @@ -190,6 +191,8 @@ object RocketTile extends SerializableModuleElaborator {
implicit def RocketTileParameterMainParser: ParserForClass[RocketTileParameterMain] =
ParserForClass[RocketTileParameterMain]

override def additionalAnnotations = Seq(IncludeUtilMetadata)

@main
def config(@arg(name = "parameter") parameter: M) =
os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert))
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3 changes: 3 additions & 0 deletions elaborator/src/t1/T1.scala
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Expand Up @@ -3,6 +3,7 @@
package org.chipsalliance.t1.elaborator.t1

import chisel3.experimental.util.SerializableModuleElaborator
import chisel3.stage.IncludeUtilMetadata
import mainargs._
import org.chipsalliance.t1.rtl.vrf.RamType
import org.chipsalliance.t1.rtl.vrf.RamType.{p0rp1w, p0rw, p0rwp1rw}
Expand Down Expand Up @@ -58,6 +59,8 @@ object T1 extends SerializableModuleElaborator {

implicit def T1ParameterMainParser: ParserForClass[M] = ParserForClass[M]

override def additionalAnnotations = Seq(IncludeUtilMetadata)

@main
def config(@arg(name = "parameter") parameter: M) =
os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert))
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3 changes: 3 additions & 0 deletions elaborator/src/t1emu/TestBench.scala
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Expand Up @@ -3,6 +3,7 @@
package org.chipsalliance.t1.elaborator.t1emu

import chisel3.experimental.util.SerializableModuleElaborator
import chisel3.stage.IncludeUtilMetadata
import mainargs._
import org.chipsalliance.t1.rtl.vrf.RamType
import org.chipsalliance.t1.rtl.vrf.RamType.{p0rp1w, p0rw, p0rwp1rw}
Expand Down Expand Up @@ -59,6 +60,8 @@ object TestBench extends SerializableModuleElaborator {

implicit def T1ParameterMainParser: ParserForClass[M] = ParserForClass[M]

override def additionalAnnotations = Seq(IncludeUtilMetadata)

@main
def config(@arg(name = "parameter") parameter: M) =
os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert))
Expand Down
3 changes: 3 additions & 0 deletions elaborator/src/t1rocket/T1RocketTile.scala
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Expand Up @@ -5,6 +5,7 @@ package org.chipsalliance.t1.elaborator.t1rocketv
import chisel3.experimental.util.SerializableModuleElaborator
import chisel3.util.BitPat
import chisel3.util.experimental.BitSet
import chisel3.stage.IncludeUtilMetadata
import mainargs._
import org.chipsalliance.t1.rtl.VFUInstantiateParameter
import org.chipsalliance.t1.rtl.vrf.RamType
Expand Down Expand Up @@ -111,6 +112,8 @@ object T1RocketTile extends SerializableModuleElaborator {
implicit def T1RocketTileParameterMainParser: ParserForClass[T1RocketTileParameterMain] =
ParserForClass[T1RocketTileParameterMain]

override def additionalAnnotations = Seq(IncludeUtilMetadata)

@main
def config(@arg(name = "parameter") parameter: M) =
os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert))
Expand Down
3 changes: 3 additions & 0 deletions elaborator/src/t1rocketemu/TestBench.scala
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Expand Up @@ -5,6 +5,7 @@ package org.chipsalliance.t1.elaborator.t1rocketemu
import chisel3.experimental.util.SerializableModuleElaborator
import chisel3.util.BitPat
import chisel3.util.experimental.BitSet
import chisel3.stage.IncludeUtilMetadata
import mainargs._
import org.chipsalliance.t1.rtl.VFUInstantiateParameter
import org.chipsalliance.t1.rtl.vrf.RamType
Expand Down Expand Up @@ -112,6 +113,8 @@ object TestBench extends SerializableModuleElaborator {
implicit def T1RocketTileParameterMainParser: ParserForClass[T1RocketTileParameterMain] =
ParserForClass[T1RocketTileParameterMain]

override def additionalAnnotations = Seq(IncludeUtilMetadata)

@main
def config(@arg(name = "parameter") parameter: M) =
os.write.over(os.pwd / s"${className}.json", configImpl(parameter.convert))
Expand Down
8 changes: 4 additions & 4 deletions nix/t1/dependencies/_sources/generated.json
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Expand Up @@ -41,7 +41,7 @@
},
"chisel": {
"cargoLocks": null,
"date": "2024-10-16",
"date": "2024-10-18",
"extract": null,
"name": "chisel",
"passthru": null,
Expand All @@ -53,11 +53,11 @@
"name": null,
"owner": "chipsalliance",
"repo": "chisel",
"rev": "d564445dbcd81c6ac3319ef9442db2d177ae124f",
"sha256": "sha256-V8CxQ5VIkk2c+7KlQIcQX6Qe2PbMZI7/q+5e4iDXajI=",
"rev": "a7a68e522ccc71d08a0a0aaea0a1460d266f2d7f",
"sha256": "sha256-+njdHbPH6MpP6uIEliLTRyanJhCIWhnA2meJl8q1rso=",
"type": "github"
},
"version": "d564445dbcd81c6ac3319ef9442db2d177ae124f"
"version": "a7a68e522ccc71d08a0a0aaea0a1460d266f2d7f"
},
"chisel-interface": {
"cargoLocks": null,
Expand Down
8 changes: 4 additions & 4 deletions nix/t1/dependencies/_sources/generated.nix
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Expand Up @@ -27,15 +27,15 @@
};
chisel = {
pname = "chisel";
version = "d564445dbcd81c6ac3319ef9442db2d177ae124f";
version = "a7a68e522ccc71d08a0a0aaea0a1460d266f2d7f";
src = fetchFromGitHub {
owner = "chipsalliance";
repo = "chisel";
rev = "d564445dbcd81c6ac3319ef9442db2d177ae124f";
rev = "a7a68e522ccc71d08a0a0aaea0a1460d266f2d7f";
fetchSubmodules = false;
sha256 = "sha256-V8CxQ5VIkk2c+7KlQIcQX6Qe2PbMZI7/q+5e4iDXajI=";
sha256 = "sha256-+njdHbPH6MpP6uIEliLTRyanJhCIWhnA2meJl8q1rso=";
};
date = "2024-10-16";
date = "2024-10-18";
};
chisel-interface = {
pname = "chisel-interface";
Expand Down