Full instruction set

The RISC-V instruction set was designed to be extremely modular. This is helpful for allowing embedded systems to imp` |lement only what they need. However it sometimes leads to confusion because things that are taken for granted, for example: timer interrupts, are actually not included in the core set, but are only available through an extension. This listing includes ALL the instructions listed in RISC-V Instruction Set Manual Volume I: Unprivileged ISA Document Version 20191213 and RISC-V Instruction Set Manual Volume II: Privileged Architecture Document Version 20211203. If a set of instructions are part of an extension that is noted above them.

The RISC-V instruction set was designed to include a small number of very powerful instructions. In fact at the time of writing it contains only instructions. This goal means that operations that can be acheived with other operations are usually not included, for example: negating a number can be acheived by subtracting that number from 0. Instead these operations are possible through a combination of smaller, simpler instructions. These combinations are well known and thus RISC-V specifies a list of assembler pseudo instructions to implement these operations. An assembler pseudo instruction will be turned into the smaller, simpler instructions by the assembler, transparently to the developer. These pseudo instructions are also included in this listing.

assembly	extension	description	example
`add`	`I`
`addi`	`I`
`addiw`	`I`
`addw`	`I`
`amoadd.d`	`A`
`amoadd.w`	`A`
`amoand.d`	`A`
`amoand.w`	`A`
`amomax.d`	`A`
`amomax.w`	`A`
`amomaxu.d`	`A`
`amomaxu.w`	`A`
`amomin.d`	`A`
`amomin.w`	`A`
`amominu.d`	`A`
`amominu.w`	`A`
`amoor.d`	`A`
`amoor.w`	`A`
`amoswap.d`	`A`
`amoswap.w`	`A`
`amoxor.d`	`A`
`amoxor.w`	`A`
`and`	`I`
`andi`	`I`
`auipc`	`I`
`beq`	`I`
`beqz`	`pseudo-instruction`
`bge`	`I`
`bgeu`	`I`
`bgez`	`pseudo-instruction`
`bgt`	`pseudo-instruction`
`bgtu`	`pseudo-instruction`
`bgtz`	`pseudo-instruction`
`ble`	`pseudo-instruction`
`bleu`	`pseudo-instruction`
`blez`	`pseudo-instruction`
`blt`	`I`
`bltu`	`I`
`bltz`	`pseudo-instruction`
`bne`	`I`
`bnez`	`pseudo-instruction`
`call`	`pseudo-instruction`
`csrc`	`pseudo-instruction`
`csrci`	`pseudo-instruction`
`csrr`	`pseudo-instruction`
`csrrc`	`Zicsr`
`csrrci`	`Zicsr`
`csrrs`	`Zicsr`
`csrrsi`	`Zicsr`
`csrrw`	`Zicsr`
`csrrwi`	`Zicsr`
`csrs`	`pseudo-instruction`
`csrsi`	`Zicsr`
`csrw`	`pseudo-instruction`
`csrwi`	`Zicsr`
`div`	`M`
`divu`	`M`
`divuw`	`M`
`divw`	`M`
`ebreak`	`I`
`ecall`	`I`
`fabs.d`	`pseudo-instruction`
`fabs.s`	`pseudo-instruction`
`fadd.d`	`D`
`fadd.q`	`Q`
`fadd.s`	`F`
`fclass.d`	`D`
`fclass.q`	`Q`
`fclass.s`	`F`
`fcvt.d.l`	`D`
`fcvt.d.lu`	`D`
`fcvt.d.q`	`D`
`fcvt.d.s`	`D`
`fcvt.d.w`	`D`
`fcvt.d.wu`	`D`
`fcvt.l.d`	`D`
`fcvt.l.q`	`Q`
`fcvt.l.s`	`F`
`fcvt.lu.d`	`D`
`fcvt.lu.q`	`Q`
`fcvt.lu.s`	`F`
`fcvt.q.d`	`Q`
`fcvt.q.l`	`Q`
`fcvt.q.lu`	`Q`
`fcvt.q.s`	`Q`
`fcvt.q.w`	`Q`
`fcvt.q.wu`	`Q`
`fcvt.s.d`	`D`
`fcvt.s.l`	`F`
`fcvt.s.lu`	`F`
`fcvt.s.q`	`Q`
`fcvt.s.w`	`F`
`fcvt.s.wu`	`F`
`fcvt.w.d`	`D`
`fcvt.w.q`	`Q`
`fcvt.w.s`	`F`
`fcvt.wu.d`	`D`
`fcvt.wu.q`	`Q`
`fcvt.wu.s`	`F`
`fdiv.d`	`D`
`fdiv.q`	`Q`
`fdiv.s`	`F`
`fence`	`RV32`
`fence`	`pseudo-instruction (yes 2)`
`fence.i`	`Zifencei`
`feq.d`	`D`
`feq.q`	`Q`
`feq.s`	`F`
`fld`	`D`
`fle.d`	`D`
`fle.q`	`Q`
`fle.s`	`F`
`flq`	`Q`
`flt.d`	`D`
`flt.q`	`Q`
`flt.s`	`F`
`flw`	`F`
`fmadd.d`	`D`
`fmadd.q`	`Q`
`fmadd.s`	`F`
`fmax.d`	`D`
`fmax.q`	`Q`
`fmax.s`	`F`
`fmin.d`	`D`
`fmin.q`	`Q`
`fmin.s`	`F`
`fmsub.d`	`D`
`fmsub.q`	`Q`
`fmsub.s`	`F`
`fmul.d`	`D`
`fmul.q`	`Q`
`fmul.s`	`F`
`fmv.d`	`pseudo-instruction`
`fmv.d.x`	`D`
`fmv.s`	`pseudo-instruction`
`fmv.w.x`	`F`
`fmv.x.d`	`D`
`fmv.x.w`	`F`
`fneg.d`	`pseudo-instruction`
`fneg.s`	`pseudo-instruction`
`fnmadd.d`	`D`
`fnmadd.q`	`Q`
`fnmadd.s`	`F`
`fnmsub.d`	`D`
`fnmsub.q`	`Q`
`fnmsub.s`	`F`
`frcsr`	`pseudo-instruction`
`frflags`	`psuedo-instruction`
`frrm`	`pseudo-instruction`
`fscsr`	`pseudo-instruction`
`fscsr`	`pseudo-instruction (see pseudo listing, there are actually 2)`
`fsd`	`D`
`fsflags`	`pseudo-instruction`
`fsflags`	`pseudo-instruction (yes 2)`
`fsgnj.d`	`D`
`fsgnj.q`	`Q`
`fsgnj.s`	`F`
`fsgnjn.d`	`D`
`fsgnjn.q`	`Q`
`fsgnjn.s`	`F`
`fsgnjx.d`	`D`
`fsgnjx.q`	`Q`
`fsgnjx.s`	`F`
`fsq`	`Q`
`fsqrt.d`	`D`
`fsqrt.q`	`Q`
`fsqrt.s`	`F`
`fsrm`	`pseudo-instruction`
`fsrm`	`pseudo-instruction (yes 2)`
`fsub.d`	`D`
`fsub.q`	`Q`
`fsub.s`	`F`
`fsw`	`F`
`hfence.gvma`	`privileged`
`hfence.vvma`	`privileged`
`hinval.gvma`	`privileged`
`hinval.vvma`	`privileged`
`hlv.b`	`privileged`
`hlv.bu`	`privileged`
`hlv.d`	`privileged`
`hlv.h`	`privileged`
`hlv.hu`	`privileged`
`hlv.w`	`privileged`
`hlv.wu`	`privileged`
`hlvx.hu`	`privileged`
`hlvx.wu`	`privileged`
`hsv.b`	`privileged`
`hsv.d`	`privileged`
`hsv.h`	`privileged`
`hsv.w`	`privileged`
`j`	`pseudo-instruction`
`jal`	`I`
`jal`	`pseudo-instruction`
`jalr`	`I`
`jalr`	`pseudo-instruction`
`jr`	`pseudo-instruction`
`la (non-pic)`	`pseudo-instruction`
`la (pic)`	`pseudo-instruction`
`lb`	`I`
`lb`	`pseudo-instruction`
`lbu`	`I`
`lbu`	`pseudo-instruction`
`ld`	`I`
`ld`	`pseudo-instruction`
`lh`	`I`
`lh`	`pseudo-instruction`
`lhu`	`I`
`lhu`	`pseudo-instruction`
`li`	`pseudo-instruction`
`lla`	`pseudo-instruction`
`lr.d`	`A`
`lr.w`	`A`
`lui`	`I `
`lw`	`I`
`lw`	`pseudo-instruction`
`lwu`	`I`
`lwu`	`pseudo-instruction`
`mret`	`privileged`
`mul`	`M`
`mulh`	`M`
`mulhsu`	`M `
`mulhu`	`M`
`mulw`	`M`
`mv`	`pseudo-instruction`
`neg`	`pseudo-instruction`
`negw`	`pseudo-instruction`
`nop`	`pseudo-instruction`
`not`	`pseudo-instruction`
`or`	`I`
`ori`	`I`
`rdcycle`	`pseudo-instruction`
`rdcycleh`	`pseudo-instruction`
`rdinstret`	`pseudo-instruction`
`rdinstreth`	`pseudo-instruction`
`rdtime`	`pseudo-instruction`
`rdtimeh`	`pseudo-instruction`
`rem`	`I`
`remu`	`I`
`remuw`	`I`
`remw`	`I`
`ret`	`pseudo-instruction`
`sb`	`I`
`sb`	`pseudo-instruction`
`sc.d`	`A`
`sc.w`	`A`
`sd`	`I`
`sd`	`pseudo-instruction`
`seqz`	`pseudo-instruction`
`sext.w`	`pseudo-instruction`
`sfence.inval.ir`	`privileged`
`sfence.vma`	`privileged`
`sfence.w.inval`	`privileged`
`sgtz`	`pseudo-instruction`
`sh`	`I`
`sh`	`pseudo-instruction`
`sinval.vma`	`privileged`
`sll`	`I`
`slli`	`I`
`slliw`	`I`
`sllw`	`I `
`slt`	`I`
`slti`	`I `
`sltiu`	`I`
`sltu`	`I`
`sltz`	`pseudo-instruction`
`snez`	`pseudo-instruction`
`sra`	`I`
`srai`	`I`
`sraiw`	`I`
`sraw`	`I`
`sret`	`priviliged`
`srl`	`I`
`srli`	`I`
`srli`	`I`
`srliw`	`I`
`srlw`	`I`
`sub`	`I`
`subw`	`I`
`sw`	`I`
`sw`	`pseudo-instruction`
`tail`	`pseudo-instruction`
`wfi`	`privileged`
`xor`	`I`
`xori`	`I`