This project presents a hardware-based implementation of the Jarvis March (Gift Wrapping) algorithm to compute the convex hull of a given set of 2D points. The circuit is designed and simulated in Proteus, demonstrating the feasibility of geometric computations in electronic systems. Each point in the input set is assigned a unique point number, and the circuit processes these coordinates to identify the boundary points forming the convex hull. The Jarvis March algorithm is implemented using combinational and sequential logic, iteratively selecting the next outermost point in a counterclockwise manner until the hull is complete. Once the convex hull is determined, the circuit calculates the sum of the point numbers of these boundary points. This sum is then displayed as the final result, showcasing a practical application of convex hull computation in digital logic design. The Proteus simulation validates the accuracy of the design, proving its effectiveness in handling geometric problems using hardware logic. This project serves as an example of integrating computational geometry with circuit design, potentially useful in fields like robotics, image processing, and pattern recognition.