(WIP) Add MF8 Regfile Example

examples/mf8/MF8A18.v

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+/*
+ * Copyright 2018 MicroFPGA UG
+ * Apache 2.0 License
+ */
+
+module MF8A18 (
+   CLK,
+   RST,
+   rom_addr,
+   rom_data,
+   maddr,
+   mwdata,
+   ramdata,
+   mwrite,
+   mread,
+   SPI_MISO,
+   SPI_MOSI,
+   SPI_SCK,
+   SPI_CS,
+   UART_TXD);
+
+
+input   CLK; 
+input   RST;
+output   [9:0] rom_addr; 
+input   [15:0] rom_data; 
+output   [15:0] maddr; 
+output   [7:0] mwdata; 
+input   [7:0] ramdata; 
+output   mwrite; 
+output   mread; 
+input   SPI_MISO; 
+output   SPI_MOSI; 
+output   SPI_SCK; 
+output   SPI_CS; 
+output   UART_TXD; 
+
+
+// 
+wire    [9:0] rom_addr; 
+wire    [15:0] maddr; 
+wire    [7:0] mwdata; 
+wire    mwrite; 
+wire    mread; 
+reg     SPI_MOSI; 
+reg     SPI_SCK; 
+reg     SPI_CS; 
+reg     UART_TXD; 
+reg     Reset_s;
+wire    Reset_s_i;
+wire    IO_Rd; 
+wire    IO_Wr; 
+wire    [5:0] IO_Addr; 
+wire    [7:0] IO_WData; 
+wire    [7:0] IO_RData; 
+
+wire    [15:0] Z; 
+wire    [7:0] ram_datain; 
+wire    ram_write; 
+
+wire    [15:0] maddr_i; 
+wire    [15:0] maddr_s; 
+wire    mread_i; 
+wire    mwrite_i; 
+
+assign maddr = maddr_i; 
+assign mread = mread_i; 
+assign mwrite = mwrite_i; 
+
+always @(posedge CLK)
+begin : process_1
+	Reset_s <= RST;
+end
+
+always @(posedge CLK)
+begin : process_2
+	if (Reset_s === 1'b 1)
+	begin
+		UART_TXD <= 1'b 1;   
+		SPI_CS   <= 1'b 1;   
+		SPI_SCK  <= 1'b 1;   
+		SPI_MOSI <= 1'b 1;   
+	end else
+	begin
+	if (IO_Wr === 1'b 1)
+	begin
+        	if (IO_Addr[4:3] === 2'b 00) begin  UART_TXD <= IO_WData[0]; end //  00 xxxxx 0x20
+		if (IO_Addr[4:3] === 2'b 01) begin  SPI_CS <= IO_WData[7];   end //  01 xxxx 0x10
+		if (IO_Addr[4:3] === 2'b 10) begin  SPI_SCK <= IO_WData[0];  end //  11 xxxx 0x20
+		if (IO_Addr[4:3] === 2'b 11) begin  SPI_MOSI <= IO_WData[7]; end //  10 xxxx 0x30
+         end
+      end
+ end
+
+assign mwdata = IO_WData; 
+
+mf8_core core (
+	.Clk		(CLK),
+        .Reset		(Reset_s),
+        .ROM_Addr	(rom_addr[9:0]),
+        .ROM_Data	(rom_data),
+        .ZZ		(maddr_i),
+        .ram_datain	(ramdata),
+        .ram_write	(mwrite_i),
+        .ram_read	(mread_i),
+        .IO_Rd		(IO_Rd),
+        .IO_Wr		(IO_Wr),
+        .IO_Addr	(IO_Addr),
+        .IO_RData	(IO_RData),
+        .IO_WData	(IO_WData)
+);
+
+assign IO_RData = {7'b 0000000, SPI_MISO}; 
+
+endmodule //

examples/mf8/MF8A18_SoC.v

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+/*
+ * Copyright 2018 MicroFPGA UG
+ * Apache 2.0 License
+ */
+
+
+module MF8A18_SoC (
+	clk,
+	reset,
+	FLASH_SCK,
+	FLASH_CS,
+	FLASH_MISO,
+	FLASH_MOSI,
+	UART_TXD
+	);
+
+	output FLASH_SCK;
+	output FLASH_CS;
+	input FLASH_MISO;
+	output FLASH_MOSI;
+
+	input clk;
+	input reset;
+	output UART_TXD;
+
+	wire [9:0] rom_addr;
+	wire [15:0] rom_data;
+
+	wire [15:0] maddr;
+	wire [7:0]  mwdata;
+	wire [7:0]  mrdata;
+	wire        mwrite;
+
+	MF8A18 cpu (
+		.CLK		(clk),
+        	.RST		(reset),
+	        .SPI_CS		(FLASH_CS),
+	        .SPI_MISO	(FLASH_MISO),
+	        .SPI_MOSI	(FLASH_MOSI),
+	        .SPI_SCK	(FLASH_SCK),
+	        .UART_TXD	(UART_TXD),
+	        .maddr		(maddr),
+	        .mread		(),
+	        .mwdata		(mwdata),
+	        .mwrite		(mwrite),
+	        .ramdata	(mrdata),
+	        .rom_addr	(rom_addr),
+	        .rom_data	(rom_data)
+	);
+
+	ROM1K16 rom (
+		.addr		(rom_addr),
+	        .clk		(clk),
+        	.dout		(rom_data)
+	);
+
+	RAM32K ram (
+		.addr		(maddr[14:0]),
+	        .clk		(clk),
+        	.din		(mwdata),
+	        .dout		(mrdata),
+	        .we		(mwrite)
+	);
+
+endmodule

examples/mf8/RAM32K.v

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+/*
+ * Copyright 2018 MicroFPGA UG
+ * Apache 2.0 License
+ */
+
+module RAM32K (clk, addr, din, dout, we);
+
+input clk;
+input we;
+input [14:0] addr;
+input  [7:0] din;
+output [7:0] dout;
+
+// RAM
+`ifdef SIM
+
+reg [7:0] mem [0:32*1024-1];
+reg [7:0] dout;
+initial $readmemh("riscv.mem", mem);
+
+always @(posedge clk) begin
+	if (we) mem[addr] <= din;
+	dout <= mem[addr];
+end
+
+`else
+
+// SBRAM
+wire [15:0] SBRAM_Dataout;
+reg DelayOdd;
+always @(posedge clk) begin
+	DelayOdd <= addr[0];
+end
+assign dout = DelayOdd? SBRAM_Dataout[15:8] : SBRAM_Dataout[7:0];
+
+SB_SPRAM256KA ram (
+    .ADDRESS(addr[14:1]),
+    .DATAIN({din, din}),
+    .MASKWREN({addr[0], addr[0], ~addr[0], ~addr[0]}),
+    .WREN(we),
+    .CHIPSELECT(1'b1),
+    .CLOCK(clk),
+    .STANDBY(1'b0),
+    .SLEEP(1'b0),
+    .POWEROFF(1'b1),
+    .DATAOUT(SBRAM_Dataout)
+);
+
+`endif
+
+endmodule

examples/mf8/ROM1K16.v

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+/*
+ * Copyright 2018 MicroFPGA UG
+ * Apache 2.0 License
+ */
+
+module ROM1K16 (clk, addr, dout);
+
+input clk;
+input [8:0] addr;
+output [15:0] dout;
+
+// ROM with a single synchronous read port (can be mapped to Block RAM)
+reg [15:0] mem [0:511];
+reg [15:0] dout;
+initial $readmemh("rv32i.mem", mem);
+always @(posedge clk) begin
+	dout <= mem[addr];
+end
+
+endmodule

examples/mf8/addsub8.v

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+/*
+ * Copyright 2018 MicroFPGA UG
+ * Apache 2.0 License
+ */
+
+
+module addsub8 (
+   a,
+   b,
+   q,
+   sub,
+   cin,
+   cout
+);
+
+
+input   [7:0] a; 
+input   [7:0] b; 
+output  [7:0] q; 
+input   sub; 
+input   cin; 
+output  cout; 
+
+wire    [7:0] q; 
+wire    cout; 
+wire    [8:0] A_i; 
+wire    [8:0] B_i; 
+wire    [8:0] Full_Carry; 
+wire    [8:0] Res_i; 
+
+assign B_i[8] = 1'b 0; 
+assign B_i[7:0] = sub === 1'b 1 ? ~b : b; 
+assign A_i[8] = 1'b 0; 
+assign A_i[7:0] = a; 
+assign Full_Carry[8:1] = 8'b 00000000; 
+assign Full_Carry[0] = cin; 
+assign Res_i = A_i + B_i + Full_Carry; 
+assign cout = Res_i[8]; 
+assign q = Res_i[7:0]; 
+
+endmodule // module addsub8
+