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extend Memory backend to dealing with various needs #147
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Hello @KotorinMinami, thanks for contribution. But I see more drawbacks there. The first and most important principle for QtRvSim is to make it illustrative for students us much as possible and the next to keep it in state, that it can be reasonably maintained and each added complexity should be backed by real needs.
So in general, there are more problems where I do not see clean profit. As for the pull request, I would prefer to divide changes to hexedit and docks change as separate commit, memory three height commit and then machine setup adjustments as separate ones. I do not see this change as priority, which is branch predictor for me and I wait for @jiristefan and @jdupak to resolve issues with me to have at least solid tool for branch prediction demonstration on single-cycle core. The pipelined cannot misbehave in the actual program results (which is actually in correct state), but tuning for more appropriate statistic in pipelined version is complex task and without predecode in cache can be hardly solved ideal way. Back to 64-bit mode. I do not see it as important for teaching, for sure, the core should behave correctly, which I hope it does, but 64-bit addresses are harder to follow, we do not have enough space in signal views, there would be great some ellipses for numbers with many zeros or F's as 0xf....f123 etc. Even in 64-bit mode, I see 4GB limit in physical address space as enough for education and experiments. Even Can you send link to your teaching materials or describe idea where full 64-bit address space is real advantage? In the fact, I would be more interested in sv39 and even more in some simpler sv32 MMU and full range wirtual address space and keep physical addressing at 32 bits for now. But my time and budget resources are very limited and realiable function of the base is more important for me than features. |
@@ -33,12 +37,16 @@ Machine::Machine(MachineConfig config, bool load_symtab, bool load_executable) | |||
} | |||
mem = new Memory(*mem_program_only); | |||
} else { | |||
mem = new Memory(machine_config.get_simulated_endian()); | |||
mem = (this->machine_config.get_simulated_xlen() == Xlen::_64 ? new Memory(machine_config.get_simulated_endian(), 64) : new Memory(machine_config.get_simulated_endian(), 32)); |
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nit: Making a function xlen to bit size would be nicer.
@@ -48,7 +48,7 @@ HexLineEdit::HexLineEdit( | |||
set_value(0); | |||
} | |||
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void HexLineEdit::set_value(uint32_t value) { | |||
void HexLineEdit::set_value(uint64_t value) { | |||
QString s, t = ""; | |||
last_set = value; | |||
s = QString::number(value, base); |
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I am fine with storing 64bit values here, but we should make more a 32 bit friendly visualization.
We know that qtrvsim uses a memorytree with a fixed depth of 6, which causes its memory model to only accept 32-bit memory access instructions, thus restricting 64-bit access. This limitation presents an issue in terms of educational rigor. Therefore, this PR makes corresponding adjustments so that the memory class adapts its memory access bit width according to xlen, while also addressing the #146