This experiment aims to design and verify an 8-tap Finite Impulse Response (FIR) filter using Verilog. The filter operates on fixed-point Q4.12 format (16-bit signed data with 4 integer bits and 12 fractional bits) and uses the following filter coefficients: [-0.0841, -0.0567, 0.1826, 0.4086, 0.4086, 0.1826, -0.0567, -0.0841]
Using the given coefficients, the FIR filter performs a convolution over 8 previous samples. On each clock cycle:
- It shifts the new input sample into a shift register.
- It calculates a dot product between stored samples and coefficients.
- The result is scaled appropriately and output in fixed-point Q4.12 format.
- The filter includes a reset input to initialize all internal states.
A Verilog testbench is used to verify the FIR filter:
- Reads hexadecimal input data from Input_Data.txt.
- Converts each input sample to floating-point and stores the recent 8 samples.
- Compute the golden output using floating-point arithmetic.
- Feeds the sample to the DUT (Device Under Test).
- Waits for one clock cycle (pipeline latency).
- Converts DUT output back to float and compares it with the golden output.
- Computes and displays the error.
- Logs results to Output_Data.txt.
- The golden reference is a high-precision floating-point model of the filter implemented in the testbench. It helps:
- Validate the correctness of the fixed-point hardware design.
- Ensure filtering behavior matches the expected theoretical model.
- Identify any mismatch or inaccuracy introduced by fixed-point operations.
The error is computed as: error = DUT_output - golden_output
This helps analyze how closely the hardware matches the software reference. Small errors are expected due to quantization, fixed-point truncation, or rounding, but large errors may indicate design flaws or misconfigurations.