base_fw: update mem_state_info TLV

This change improves the TLV assembly algorithm in accordance with how the part for hpsram is assembled. In the case when ebb_state_dword_count is equal to 0, we skip adding the LSPGCTL register value for lpsram. Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
dnikodem · Feb 19, 2024 · dfd114f · dfd114f
1 parent ac4cf61
commit dfd114f
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Showing 4 changed files with 10 additions and 4 deletions.
diff --git a/src/audio/base_fw.c b/src/audio/base_fw.c
@@ -222,11 +222,13 @@ static int basefw_mem_state_info(uint32_t *data_offset, char *data)
 	index = 0;
 	tuple_data[index++] = info.free_phys_mem_pages;
 	tuple_data[index++] = info.ebb_state_dword_count;
+	for (i = 0; i < info.ebb_state_dword_count; i++) {
 #ifdef INTEL_ADSP
-	tuple_data[index++] = io_reg_read(LSPGCTL);
+		tuple_data[index + i] = io_reg_read(SHIM_LSPGCTL(i));
 #else
-	tuple_data[index++] = 0;
+		tuple_data[index + i] = 0;
 #endif
+	}
 	tuple_data[index++] = info.page_alloc_struct.page_alloc_count;
 	ptr = (uint16_t *)(tuple_data + index);
 	for (i = 0; i < info.page_alloc_struct.page_alloc_count; i++)

diff --git a/src/platform/lunarlake/include/platform/lib/shim.h b/src/platform/lunarlake/include/platform/lib/shim.h
@@ -47,7 +47,8 @@
 #define L2HSBPM(x)			(0x17A800 + 0x0008 * (x))
 #define SHIM_HSPGCTL(x)			(L2HSBPM(x) + 0x0000)
 
-#define LSPGCTL				0x71D80
+#define LSPGCTL0		0x71D80
+#define SHIM_LSPGCTL(x)		(LSPGCTL0 + 0x0008 * (x))
 
 #endif /* __PLATFORM_LIB_SHIM_H__ */
 

diff --git a/src/platform/meteorlake/include/platform/lib/shim.h b/src/platform/meteorlake/include/platform/lib/shim.h
@@ -47,7 +47,8 @@
 #define L2HSBPM(x)			(0x17A800 + 0x0008 * (x))
 #define SHIM_HSPGCTL(x)			(L2HSBPM(x) + 0x0000)
 
-#define LSPGCTL				0x71D80
+#define LSPGCTL0		0x71D80
+#define SHIM_LSPGCTL(x)		(LSPGCTL0 + 0x0008 * (x))
 
 #endif /* __PLATFORM_LIB_SHIM_H__ */
 

diff --git a/src/platform/tigerlake/include/platform/lib/shim.h b/src/platform/tigerlake/include/platform/lib/shim.h
@@ -243,6 +243,8 @@
 #define LSRMCTL			0x71D54
 #define LSPGISTS		0x71D58
 
+#define SHIM_LSPGCTL(x)		LSPGCTL
+
 #define SHIM_L2_MECS		(SHIM_BASE + 0xd0)
 
 /** \brief LDO Control */