Introduce control to relax memory ordering semantics for atomics on Intel HW#42
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eternastudento wants to merge 1 commit intodoitsujin:mainfrom
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Introduce control to relax memory ordering semantics for atomics on Intel HW#42eternastudento wants to merge 1 commit intodoitsujin:mainfrom
eternastudento wants to merge 1 commit intodoitsujin:mainfrom
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…ntel HW DX specification does not mention any additional synchronization requirements for atomics, e.g.: https://learn.microsoft.com/en-us/windows/win32/direct3dhlsl/atomic-iadd--sm5---asm- Therefore the semantics could be relaxed for certain HW to not introduce additional synchronization.
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I really don't want to add hardware-specific paths here. I'm aware that this is still an issue, but I'm busy with far too many non-dxvk things at the moment to really look into this, I simply don't have the time to deal with this properly at the moment. Either way, adding config hacks to work around suboptimal code gen without understanding why the supposedly optimal thing breaks in certain game/driver combinations isn't really acceptable unless this issue is very high priority for some reason (i.e. things are broken/unusable on current Experimental or something). I want this code to remain maintainable, changing things in such a way that it potentially creates more hardware-specific issues in the long run is the opposite of that. |
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DX specification does not mention any additional synchronization requirements for atomics, e.g.:
https://learn.microsoft.com/en-us/windows/win32/direct3dhlsl/atomic-iadd--sm5---asm-
Therefore the semantics could be relaxed for certain HW to not introduce additional synchronization.
To be followed with dxvk change to set the flag on Intel HW.