v1.6.1: Coremark

• Pass Coremark benchmark, 2.78 coremark/MHz
• Update synthesis flow

v1.6.0: Add user-mode support

Put in place a MPU to support user-mode and PMP/PMA features

v1.5.1

• Populate IO / parameters chapter
• Clean-up README files
• JAL doesn't wait for processing to be ready to jump.

CPI = 2.03

v1.5.0

New release to enhance performance. CPI = 2 now, many work done in AXI4-lite infrastructure, in memfy and dCache.

Full Changelog: v1.4.0...v1.5.0

v1.4.0

Misc. code updates and simplification to enhance performance.

• control is simpler and can flush request and reboot on same cycle.
• separates block fetcher and prefetch on cache miss
• simplify icache sequencer
• CSR executes in one cycle
• processing schedules multiples instructions in same cycles if no hazards
• memfy better manages outstanding requests

Misc Fixes

Contains misc. updates related to dCache development
REPL app flow up with bench function and a new (simple) printf implmentation

v1.3.0 - dCache

New release introducing bunch of updates and features, the biggest being a dCache.

Introduce an internal AXI4 Crossbar

This release introduces a new top level, the platform, integrating the core and an AXI4 Crossbar to add peripherals and later more harts. Adding the crossbar will permit to add peripheral easily like an interrupt controller and start to create the software platform.

v1.1.0: New: Deploy the new trap handling system

    - mtvec now support direct & vectored mode
    - mtval is also written by control unit
    - load/store misalignment is better implemented