more updates on the transpilation logic during compilation

src/qrisp/core/compilation.py

@@ -88,6 +88,9 @@ def reordering_transpile_predicate(op):
             if isinstance(op, (LogicSynthGate, GidneyLogicalAND, JonesToffoli, QuasiRZZ)):
                 return False
 
+            if "QFT" == op.name[:3]:
+                return False
+
             return True
 
 
@@ -108,14 +111,6 @@ def parallellization_transpile_predicate(op):
 
         qc = parallelize_qc(qc, depth_indicator = gate_speed)
 
-        if cancel_qfts:
-            # The first step is to cancel adjacent QFT gates, which are inverse to each
-            # other. This can happen alot because of the heavy use of Fourier arithmetic
-
-
-            qc = transpile(qc, transpile_predicate=qft_transpile_predicate)
-
-            qc = qft_cancellation(qc)
 
         if intended_measurements:
             # This function reorders the circuit such that the intended measurements can
@@ -153,10 +148,32 @@ def parallellization_transpile_predicate(op):
         )
         reordered_qc = reorder_qc(transpiled_qc)
 
+        if cancel_qfts:
+            # The first step is to cancel adjacent QFT gates, which are inverse to each
+            # other. This can happen alot because of the heavy use of Fourier arithmetic
+
+            reordered_qc = transpile(reordered_qc, transpile_predicate=qft_transpile_predicate)
+
+            reordered_qc = qft_cancellation(reordered_qc)
+
+
+
+        def logic_synth_transpile_predicate(op):
+
+            if isinstance(op, PTControlledOperation):
+
+                if op.base_operation.name == "x":
+                    return False
+
+            if isinstance(op, (LogicSynthGate, GidneyLogicalAND, JonesToffoli)):
+                return False
+
+            return True
+
         # Transpile logic synthesis
         reordered_qc = transpile(
             reordered_qc,
-            transpile_predicate=reordering_transpile_predicate,
+            transpile_predicate=logic_synth_transpile_predicate,
         )
 
         # We combine adjacent single qubit gates

src/qrisp/logic_synthesis/gray_synthesis.py

@@ -433,7 +433,7 @@ def __init__(self, target_phases, phase_tolerant = False):
 
         self.abstract_params = set()
         for i in range(len(target_phases)):
-            if not isinstance(target_phases[i], (int, float)):
+            if not isinstance(target_phases[i], (int, float, np.float64)):
                 self.abstract_params = self.abstract_params.union(target_phases[i].free_symbols)
 
     def control(self, num_ctrl_qubits=1, ctrl_state=-1, method=None):