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Miatoll: Update AcpiTables
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@Icesito68
Icesito68 committed Sep 30, 2023
1 parent 22359e2 commit a23d912
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Showing 9 changed files with 73 additions and 54 deletions.
2 changes: 1 addition & 1 deletion Platform/EFI_Binaries
Submodule EFI_Binaries updated 116 files
19 changes: 12 additions & 7 deletions Platform/Xiaomi/sm7125/miatoll.fdf.inc
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Expand Up @@ -6,13 +6,18 @@ FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD {
# Customized DSDT
SECTION RAW = Platform/Xiaomi/sm7125/AcpiTables/miatoll/DSDT.aml
# Common Tables
# SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/DBG2.aml
SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/FACP.aml
SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/GTDT.aml
# SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/IORT.aml
SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/MADT.aml
SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/PPTT.aml
SECTION UI = "AcpiTables"
SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/APIC.aml
SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/CSRT.aml
SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/DBG2.aml
SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/FACP.aml
SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/FACS.aml
SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/GTDT.aml
SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/IORT.aml
SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/MCFG.aml
SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/PPTT.aml
SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/SPCR.aml
SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/TPM2.aml
SECTION UI = "AcpiTables"
}


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0 ...alcomm/sm7125/AcpiTables/BuiltIn/MADT.aml → ...alcomm/sm7125/AcpiTables/BuiltIn/APIC.aml
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Binary file added Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/CSRT.aml
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Binary file added Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/FACS.aml
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Binary file added Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/MCFG.aml
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Binary file added Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/SPCR.aml
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Binary file added Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/TPM2.aml
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106 changes: 60 additions & 46 deletions Silicon/Qualcomm/sm7125/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.c
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Expand Up @@ -4,68 +4,81 @@
static ARM_MEMORY_REGION_DESCRIPTOR_EX gDeviceMemoryDescriptorEx[] = {
/* Name Address Length HobOption ResourceAttribute ArmAttributes
ResourceType MemoryType */

/* DDR Regions */
{"Hypervisor", 0x80000000, 0x00600000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, /* Added */
// Check: RFSLocateAndProtectSharedArea will get called
/* DDR Regions */
{"HYP", 0x80000000, 0x00600000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, /* Added */
{"MPSS_EFS", 0x80600000, 0x00200000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, UNCACHED_UNBUFFERED_XN},
{"AOP Image", 0x80800000, 0x00020000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN},
{"AOP Image", 0x80800000, 0x00020000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, /* Added */
{"AOP CMD DB", 0x80820000, 0x00020000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN},
{"GPU PRR", 0x80840000, 0x00010000, AddMem, MEM_RES, WRITE_COMBINEABLE, Reserv, UNCACHED_UNBUFFERED_XN},
{"HLOS 1", 0x80850000, 0x000AF000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN},
{"SEC APPs", 0x808FF000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, UNCACHED_UNBUFFERED_XN},
{"SMEM", 0x80900000, 0x00200000, AddMem, MEM_RES, WRITE_COMBINEABLE, Reserv, UNCACHED_UNBUFFERED},
{"TZ", 0x80B00000, 0x01700000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE},
// secapp-region
{"TZApps", 0x82200000, 0x02200000, NoHob, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE},
{"PIL_REGION", 0x84400000, 0x0F800000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, UNCACHED_UNBUFFERED_XN},
{"HLOS 2", 0x93C00000, 0x08400000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN},
{"RAM Partition", 0x80850000, 0x000AF000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN},
{"TZApps", 0x808ff000, 0x00001000, NoHob, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE},
{"SMEM", 0x80900000, 0x00200000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED},
{"QSEE", 0x80B00000, 0x03900000, NoHob, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE},
{"HLOS Entry1", 0x84400000, 0x01700000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, UNCACHED_UNBUFFERED_XN},
{"PIL Reserved", 0x85B00000, 0x0EB00000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN},
{"DXE Heap", 0x94600000, 0x04500000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN},
{"DBI Dump", 0x98B00000, 0x00D70000, NoHob, MMAP_IO, INITIALIZED, Conv, UNCACHED_UNBUFFERED_XN},
{"HLOS Entry2", 0x99870000, 0x01F90000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN},
{"Sched Heap", 0x9B800000, 0x00400000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN},
{"RAM Partition", 0x9BC00000, 0x00400000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN},
{"Display Reserved", 0x9C000000, 0x01800000, AddMem, MEM_RES, SYS_MEM_CAP, Reserv, WRITE_THROUGH_XN},
{"Runtime Data", 0x9D800000, 0x00080000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN},
{"Runtime Code", 0x9D880000, 0x00080000, AddMem, SYS_MEM, SYS_MEM_CAP, RtCode, WRITE_BACK_XN},
{"HLOS 3", 0x9D900000, 0x00700000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN},
// qseecom_mem
{"TGCM", 0x9E000000, 0x01400000, AddMem, MEM_RES, WRITE_COMBINEABLE, Reserv, UNCACHED_UNBUFFERED_XN},
{"HLOS 4", 0x9F400000, 0x00400000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN},
{"FV Region", 0x9F800000, 0x00400000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN},
{"RAM Partition", 0x9D800000, 0x00400000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN},
{"ADSP RPC", 0x9DC00000, 0x00800000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN},
{"TGCM", 0x9E400000, 0x01400000, AddMem, MEM_RES, WRITE_COMBINEABLE, Reserv, UNCACHED_UNBUFFERED_XN},
{"FV Region", 0x9F800000, 0x00200000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN},
{"RAM Partition", 0x9FA00000, 0x00200000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN},
{"UEFI FD", 0x9FC00000, 0x00300000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK},
{"SEC Heap", 0x9FF00000, 0x0008C000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN},
{"CPU Vectors", 0x9FF8C000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK},
{"MMU PageTables", 0x9FF8D000, 0x00003000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN},
{"UEFI Stack", 0x9FF90000, 0x00040000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN},
{"USB UCSI Temp", 0x9FF90000, 0x00002000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, UNCACHED_UNBUFFERED_XN},
{"RAM Partition", 0x9FF92000, 0x0001E000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN},
{"UEFI Stack", 0x9FFB0000, 0x00020000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN},
{"RSRV1", 0x9FFD0000, 0x0000A000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN},
{"TPMControl", 0x9FFDA000, 0x00003000, AddMem, MEM_RES, WRITE_COMBINEABLE, RtData, UNCACHED_UNBUFFERED_XN},
{"Reset Data", 0x9FFDD000, 0x00004000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, UNCACHED_UNBUFFERED_XN},
{"RSRV3", 0x9FFE1000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN},
{"Capsule Header", 0x9FFE2000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, UNCACHED_UNBUFFERED_XN},
{"RSRV2", 0x9FFE3000, 0x00014000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN},
{"Log Buffer", 0x9FFF7000, 0x00008000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN},
{"Info Blk", 0x9FFFF000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN},


/**************************************************
* *
* RamPartitionDXE will add MLVM regions Later. *
* 0xA0000000 to MEMORY_HOLE_START_ADDR *
* *
**************************************************/
// {"Hypervisor", 0x85700000, 0x00600000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, /* Added */
// {"TZ", 0x86200000, 0x01800000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, /* Added */
// {"RAM Partition", 0x89B00000, 0x01C00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN},
// {"RAM Partition", 0x9FF92000, 0x0001E000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN},

// Note: Runtime memory has to be on an alignment of 0x10000
{"RSRV1", 0x9FFD0000, 0x0000A000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN},
{"TPMControl", 0x9FFDA000, 0x00003000, AddMem, MEM_RES, WRITE_COMBINEABLE, Reserv, UNCACHED_UNBUFFERED_XN},
{"Reset Data", 0x9FFDD000, 0x00004000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, UNCACHED_UNBUFFERED_XN},
{"RSRV3", 0x9FFE1000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN},
{"Capsule Header", 0x9FFE2000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, UNCACHED_UNBUFFERED_XN},
{"RSRV2", 0x9FFE3000, 0x00014000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN},
{"Log Buffer", 0x9FFF7000, 0x00008000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN},
{"Info Blk", 0x9FFFF000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN},
// {"Secure DSP", 0xA0000000, 0x01200000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN},
// {"Kernel", 0xA1200000, 0x08000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN},
// {"MLVM_APSS", 0xA9200000, 0x03A00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN},
// {"MLVM_1", 0xACC00000, 0x0FC00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN},

//6GB
// Memory hole: 0xBC800000 - 0xBFFFFFFF BC800000
// Size: 0x33FFFFF

/* RAM partition regions */
{"Secure DSP", 0xA0000000, 0x01200000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN},
{"DXE Heap", 0xA1200000, 0x1B700000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN},
/* Memory hole */
/* 0xBC900000 - 0xBFFFFFFF */
{"DBI Dump", 0xC0000000, 0x00F00000, NoHob, MMAP_IO, INITIALIZED, Reserv, UNCACHED_UNBUFFERED_XN},
{"RAM Partition", 0xC0F00000, 0x0D100000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN},
{"UEFI FD", 0xCE000000, 0x02000000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK},
{"RAM Partition", 0xD0000000, 0xB0000000, Mem6G, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN},
{"RAM Partition", 0x0C0000000, 0x40000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN},
{"RAM Partition", 0x100000000, 0x80000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN},

/* Only need to map 4GB */

{"RAM Partition", 0x180000000, 0x20000000, Mem6G, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN},
{"RAM Partition", 0x1a0000000, 0x20000000, Mem6G, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN},
{"RAM Partition", 0x1c0000000, 0x20000000, Mem6G, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN},
{"RAM Partition", 0x1e0000000, 0x20000000, Mem6G, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN},
// {"RAM Partition", 0x180000000, 0x80000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN},

/* Other memory regions */
{"AOP_SS_MSG_RAM", 0x0C300000, 0x00100000, NoHob, MMAP_IO, INITIALIZED, Conv, NS_DEVICE},
{"IMEM Base", 0x14680000, 0x0002B000, NoHob, MMAP_IO, INITIALIZED, Conv, NS_DEVICE},
{"IMEM Cookie Base", 0x146AA000, 0x00001000, AddDev, MMAP_IO, INITIALIZED, Conv, NS_DEVICE},

/* Register regions */
{"GCC_CLK_CTL", 0x00100000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"GCC CLK CTL", 0x00100000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"SECURITY CONTROL", 0x00780000, 0x00007000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"PRNG_CFG_PRNG", 0x00790000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"SDC1_REG", 0x007C0000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
Expand All @@ -74,7 +87,7 @@ static ARM_MEMORY_REGION_DESCRIPTOR_EX gDeviceMemoryDescriptorEx[] = {
{"UFS UFS REGS", 0x01D80000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"CRYPTO0 CRYPTO", 0x01DC0000, 0x00040000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"TCSR_TCSR_REGS", 0x01FC0000, 0x00040000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"TLMM_EAST", 0x03500000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"TLMM_WEST", 0x03500000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"TLMM_NORTH", 0x03900000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"TLMM_SOUTH", 0x03D00000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"GPU_CC", 0x05090000, 0x00009000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
Expand All @@ -89,6 +102,7 @@ static ARM_MEMORY_REGION_DESCRIPTOR_EX gDeviceMemoryDescriptorEx[] = {
{"PDC_DISP_SEQ", 0x0B4A0000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"RPMH_BCM_BCM_TOP", 0x0BA00000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"SLP_CNTR_TSENS", 0x0C221000, 0x00003000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"TSENS0_TM_PSHOLD", 0x0C263000, 0x00003000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"PMIC ARB SPMI", 0x0C400000, 0x02800000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"VIDEO_CC", 0x0AB00000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"NPU_CC", 0x09980000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
Expand All @@ -100,7 +114,7 @@ static ARM_MEMORY_REGION_DESCRIPTOR_EX gDeviceMemoryDescriptorEx[] = {
{"APSS_RSC_RSCCR", 0x18200000, 0x00030000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"APSS_GIC500_GICD", 0x17A00000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"APSS_GIC500_GICR", 0x17A60000, 0x00100000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"QTIMER", 0x17C00000, 0x00110000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"QTIMER", 0x17C20000, 0x00110000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"APSS_ACTPM_WRAP", 0x18300000, 0x000B0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"MDSS", 0x0AE00000, 0x00134000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
{"SMMU", 0x15000000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},
Expand All @@ -111,4 +125,4 @@ static ARM_MEMORY_REGION_DESCRIPTOR_EX gDeviceMemoryDescriptorEx[] = {
ARM_MEMORY_REGION_DESCRIPTOR_EX *GetPlatformMemoryMap()
{
return gDeviceMemoryDescriptorEx;
}
}

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