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edneymatheus/README.md

👋 Hey there, I'm Édney Freitas!

⚙️ Electrical Engineer | Master's Student in Microelectronics (USP)

"From electromagnetic waves to microchips – building innovation one bit at a time."

🌐 Let's connect

🔧 IC Design & Simulation Tools

📡 SDR & RF Tools

💻 Programming Languages & Productivity Tools

📌 Featured Projects

  • 🔬 SD-VNA: Vector Network Analyzer using BladeRF + Python
  • 🛰️ Sweep Generator: Frequency sweep generator for antenna analysis
  • 🧠 Common Source Amplifier: Full analog IC flow with Magic, Ngspice, and GDS

"Simplicity and precision in every bit."

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  1. ams-counter-xschem-tutorial ams-counter-xschem-tutorial Public

    Open-source AMS co-simulation tutorial: Verilog counter + Xschem + ngspice (XSPICE d_cosim) + Icarus Verilog, with an analog testbench and step-by-step setup.

    Shell